TPS65070-Q1

Manufacturer Part NumberTPS65070-Q1
DescriptionSingle Chip Power Solution for Battery Powered Systems
ManufacturerTI1 [Texas Instruments]
TPS65070-Q1 datasheet
 


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Single Chip Power Solution for Battery Powered Systems
Check for Samples: TPS65070-Q1, TPS65072-Q1, TPS65073-Q1,
FEATURES
1
Qualified for Automotive Applications
2
Charger/Power Path Management:
– 2A Output Current on the Power Path
– Linear Charger; 1.5A Maximum Charge
Current
– 100mA/500mA/ 800mA/1300mA Current
Limit From USB Input
– Thermal Regulation, Safety Timers
– Temperature Sense Input
3 Step-Down Converters:
– 2.35MHz Fixed Frequency Operation
– Up to 1.5A of Output Current
– Adjustable or Fixed Output Voltage
– V
Range From 2.8V to 6.3V
IN
– Power Save Mode at Light Load Current
– Output Voltage Accuracy in PWM Mode
±1.5%
– Typical 19 mA Quiescent Current per
Converter
– 100% Duty Cycle for Lowest Dropout
LDOs:
– Fixed Output Voltage
– Dynamic Voltage Scaling on LDO2
– 20mA Quiescent Current
– 200mA Maximum Output Current
– V
Range From 1.8V to 6.3V
IN
wLED Boost Converter:
– Internal Dimming Using I2C
– Up to 2 × 10 LEDs
– Up to 25mA per String With Internal Current
Sink
2
I
C Interface
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732-Q1
TPS650732-Q1
10 Bit A/D Converter
Touch Screen Interface
Undervoltage Lockout and Battery Fault
Comparator
APPLICATIONS
Portable Navigation Systems
Low-Power DSP Supply
DESCRIPTION
The TPS6507x are single chip Power Management
ICs for portable applications consisting of a battery
charger with power path management for a single
Li-Ion or Li-Polymer cell. The charger can either be
supplied by a USB port on pin USB or by a dc voltage
from a wall adapter connected to pin AC. Three
highly efficient 2.25MHz step-down converters are
targeted at providing the core voltage, memory and
I/O voltage in a processor based system. The
step-down converters enter a low power mode at light
load for maximum efficiency across the widest
possible range of load currents. For low noise
applications the devices can be forced into fixed
frequency PWM using the I
step-down converters allow the use of small inductors
and capacitors to achieve a small solution size. The
TPS6507x also integrate two general purpose LDOs
for an output current of 200mA. These LDOs can be
used to power an SD-card interface and an
always-on rail, but can be used for other purposes as
well. Each LDO operates with an input voltage range
between 1.8V and 6.3V allowing them to be supplied
from one of the step-down converters or directly from
the main battery. An inductive boost converter with
two programmable current sinks power two strings of
white LEDs.
The TPS6507x come in a 48-pin leadless package
(6mm × 6mm QFN) with a 0.4mm pitch.
Copyright © 2011, Texas Instruments Incorporated
SLVSAP7 – JANUARY 2011
2
C interface. The

TPS65070-Q1 Summary of contents

  • Page 1

    ... Single Chip Power Solution for Battery Powered Systems Check for Samples: TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, FEATURES 1 • Qualified for Automotive Applications 2 • Charger/Power Path Management: – 2A Output Current on the Power Path – Linear Charger; 1.5A Maximum Charge Current – 100mA/500mA/ 800mA/1300mA Current Limit From USB Input – ...

  • Page 2

    ... Internal sequencing 0.6A / 0.6A / 1.5A 1.8V / 1.8V VQFN-48 RSL Internal sequencing (1) DERATING FACTOR T = 70°C A ABOVE T = 25°C POWER RATING A 26 mW/K 1.48 W :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com TOP-SIDE (1) PART NUMBER MARKING Reel of 2500 TPS65070TRSLRQ1 Preview Reel of 2500 TPS65072TRSLRQ1 Preview Reel of 2500 TPS65073TRSLRQ1 Preview Reel of 2500 TPS650731TRSLRQ1 ...

  • Page 3

    ... J (1) 6 VSYS whichever is less (2) See application section for more details (3) For proper soft-start Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732-Q1 (2) (2) (2) (2) (2) :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 MIN NOM MAX UNIT 4. 4.30 5.8 3 ...

  • Page 4

    ... Voltage at the output of the power manager detected at pin SYS; falling voltage, voltage defined with <UVLO0>, <UVLO1> DEFAULT: 3.0V Rising voltage defined with <UVLO hysteresis>; DEFAULT: 500mV Due to internal delay Increasing junction temperature Decreasing junction temperature :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com = 25°C (unless A MIN TYP MAX UNIT 2 ...

  • Page 5

    ... Vin > 2.8 V TPS65070 VINDCDC2 = 2.8 V VINDCDC2 = 3.5 V VINDCDC2 = 6.3 V VINDCDC2 = 2.8 V VINDCDC2 = 3 6 TPS65072/73/731/732 2.8 V < V INDCDC2 TPS65070 External resistor divider Internal resistor divider, I selectable (Default setting) :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 MIN TYP MAX UNIT 2.8 6.3 V 600 mA 150 300 mΩ 120 200 2 ...

  • Page 6

    ... Internal resistor divider, I selectable (Default setting) For DEFDCDC3 = LOW For DEFDCDC3 = HIGH For DEFDCDC3 = LOW For DEFDCDC3 = HIGH For DEFDCDC3 = LOW For DEFDCDC3 = HIGH (1) VINDCDC3 = 2 6 ≤ I ≤ 1.5 A (1) O :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com MIN TYP MAX UNIT 1.8 3.3 1.8 2.5 1.2 1.8 –2% 3% –1.5 1 ...

  • Page 7

    ... VINDCDC3 = VDCDC3 +0.3 V (min 2 6 ≤ mA, PFM mode OUT Time from active EN to Start switching Time to ramp from OUT rising voltage falling voltage :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 MIN TYP MAX UNIT –2% 3% ≤ 1.5A – ...

  • Page 8

    ... ILDO1 = 100 mA; ILDO2 = 100 mA; Vin ≥ Vout + 200 0.5 V (min. 2 6.5 V, INLDO1,2 LDO1,2 ILDO1 = 100 mA; ILDO2 = 100 200 < < Time to ramp from OUT :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com MIN TYP MAX UNIT (1) 1.8 6.3 V 1.0 3.3 V 0.725 3.3 V ...

  • Page 9

    ... Internal timer mA, Vthreshold < 0.1 mA; optional push pull output OH Reset, PB_OUT, PGood, INT open drain output in high impedance state Input voltage falling Input voltage rising :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 MIN TYP MAX UNIT 2 ...

  • Page 10

    ... AC detected when V(AC)–V(BAT) > VIN(DT) ; USB detected when V(USB)–V(BAT) > VIN(DT) AC not detected when V(AC)–V(BAT) < VIN(NDT) ; USB not detected when V(USB)–V(BAT) < VIN(NDT) Activated based on settings in CHGCONFIG3 Bit 0 and Bit 7 :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com MIN TYP MAX UNIT 0 2.25 ...

  • Page 11

    ... All power path switches set to OFF SYS(SC1) Internal resistor connected from AC to SYS; Specified by design Internal resistor connected from USB to SYS; Specified by design Set with Bits <PowerPath DPPM threshold1>; <PowerPath DPPM threshold0> :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 MIN TYP MAX UNIT 22 ...

  • Page 12

    ... Maximum value for pre-charge safety timer, thermal, DPM or DPPM loops always active 10 k curve 2 NTC 100 k curve 1 NTC Battery charging Battery charging Battery charging Battery charging NTC error Battery charging :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com MIN TYP MAX UNIT 2 A –1% 4.10 1% – ...

  • Page 13

    ... PGND3 30 SYS 7 VDCDC3 29 SYS 8 SCLK 28 ISET 9 SDAT PGOOD PB_IN 25 USB 12 PIN FUNCTIONS DESCRIPTION :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 MIN TYP MAX UNIT 115 125 135 °C 155 °C 20 °C ISET2 36 ISET1 35 ISINK1 34 ISINK2 33 VIN_DCDC3 POWER PAD ...

  • Page 14

    ... Enable input for TPS6507x. When pulled LOW, the DCDC converters and LDOs start with the sequencing PB_IN programmed internally. Internal 50kΩ pull-up resistor to AVDD6 14 Submit Documentation Feedback Product Folder Link(s) PIN FUNCTIONS (continued) DESCRIPTION :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com Copyright © 2011, Texas Instruments Incorporated ...

  • Page 15

    ... RESET 39 O THRESHOLD. PowerPAD™ Power ground connection for the PMU. Connect to GND Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732-Q1 PIN FUNCTIONS (continued) DESCRIPTION :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 Submit Documentation Feedback 15 ...

  • Page 16

    ... DCDC3 STEP-DOWN CONVERTER 600mA / 1500mA LDO1 200mA LDO LDO2 200mA LDO wLED boost I2C controlled up to 25mA per string - delay + PGND(PAD) AGND :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com SYS SYS AVDD6 4 Batt Batt TS INT_LDO BYPASS SCLK SDAT ...

  • Page 17

    ... Scope plot 3.6V; V =1.8V Scope plot 3.6V; V =1.8V Scope plot Scope plot 1.2V; V =3. Scope plot 2 x 6LEDs (VLED=19.2V 6LEDs (VLED=19.2V); I :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 FIGURE 3.3V 3. 1.8V 3. 1.2V ...

  • Page 18

    ... LOAD CURRENT/PFM MODE 100 0.0001 0.001 :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com EFFICIENCY DCDC1 vs 3.4V 3. PWM Mode 25°C 0.01 0 Output Current - A O Figure 2. EFFICIENCY DCDC2 PWM Mode 25° ...

  • Page 19

    ... LOAD CURRENT/PFM MODE 100 PWM Mode 90 25° 3. 0.0001 0.001 :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 EFFICIENCY DCDC2 PWM Mode 25°C 0.01 0 Output Current - A O Figure 6. EFFICIENCY DCDC3 vs 4.2V 5V 0.01 0.1 ...

  • Page 20

    ... LOAD TRANSIENT RESPONSE V DCDC2 (Offset: 1.8 V) OUT I DCDC2 Load :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com EFFICIENCY DCDC3 vs 3V 4.2V 5V 0.01 0 Output Current - A O Figure 10. CONVERTER 2 V DCDC3 = 3 Load mA - 1350 mA - 150 mA Figure 12. Copyright © 2011, Texas Instruments Incorporated ...

  • Page 21

    ... LINE TRANSIENT RESPONSE V DCDC1 (Offset: 3.25 V) OUT V DCDC1 (Offset LINE TRANSIENT RESPONSE V DCDC3 (Offset: 1.16 V) OUT V DCDC3 (Offset :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 CONVERTER 3 3.6V, IN Load = 0.6 A Figure 14. CONVERTER 3 3.6V, IN Load = 1.5 A Figure 16. Submit Documentation Feedback ...

  • Page 22

    ... V DCDC2 (Offset: 1.8 V) OUT I DCDC2 L LOAD TRANSIENT RESPONSE LDO1 V LDO1 (Offset: 1.8 V) OUT I LDO1 V = 3.6 V LOAD IN :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com CONVERTER 2 – PFM MODE Load = 15 mA PFM Figure 18 LDO1 = 3.6 V, bat IN LOAD = 180 mA Figure 20. Copyright © 2011, Texas Instruments Incorporated ...

  • Page 23

    ... LEDs 20 mA each 2.8 3 100 :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 K SET vs R ISET 1 10 100 Iset Figure 22. wLED EFFICIENCY vs Vin 100% duty cycle 75% duty cycle 50% duty cycle 25% duty cycle 3 ...

  • Page 24

    ... Opamp USB1300 V LOWV I USB BAT - SC t DGL(NO -IN) t DGL(PGOOD ) t BLK(OVP ) Charge control Timer fault CC1 3 CC1 0 RST EN Figure 25. Charger Block Diagram :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com 250 mV V BAT SYS - SC2 t DGL(SC2 ) VSYS ADC2 V ISET V IPRECHG ADC5 VI CHG I PRECHG ...

  • Page 25

    ... TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732-Q1 . During the power down mode the host commands at the control pins are Figure 26. Power Path Functionality is turned on till the voltage on the BAT pin rises above V BAT(SC) :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 and UVLO , DGL(PGOOD) ...

  • Page 26

    ... OUT pin, if any). In this case, the charger (Vset-100mV), a check is performed to see whether the battery RCH is pulled from the battery for a duration t :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com DONE TERM CURRENT = 1 . The battery voltage CHG BAT(REG) ...

  • Page 27

    ... RCH is pulled from the battery for t BAT(DET whichever is lesser. Battery detection is not performed. CHG IN-MAX Figure 28. :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 out of the BAT PRECHG , it is possible that a fully charged RCH : if the voltage falls below DET IN-LOW ...

  • Page 28

    ... CV TAPER REGULATION CHARGE Battery Current IC junction temperature, T Figure 28. Thermal Loop in time t during pre-charging LOWV PRECHG in time t in fast charge (measured from beginning of fast TERM MAXCH :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com DONE TERM CURRENT = 1 J Copyright © 2011, Texas Instruments Incorporated ...

  • Page 29

    ... TEMP_HOT = 1 || TEMP_COLD = 1 || TSHUT=1 DPRCHF=0 Timeout = 1 PRCH_D = 1 NO YES TAPER_D = 1 YES Clear safety timer EN_CHG=0 RECHARGE EN_CHG=0 NO RCH_D = 1 YES BAT_SRHT_D = 1 YES EN_ISHRT=1 for Tdet Figure 29. Charger State Machine :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 EN_CHG=0 FAULT EN_CHG=0 FAULT Submit Documentation Feedback 29 ...

  • Page 30

    ... The transition from PWM Mode to PFM Mode occurs once the inductor current in the Low Side MOSFET switch becomes 0. 30 Submit Documentation Feedback Product Folder Link(s) Table 1. Table 1. Default Voltages DCDC2 DEFDCDC2=HIGH DEFDCDC3=LOW :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com DCDC3 DEFDCDC3=HIGH Copyright © 2011, Texas Instruments Incorporated ...

  • Page 31

    ... Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732-Q1 +1%, the device starts a PFM pulse. For this the High Side OUTnominal Figure 30. Power Save Mode + R ) max L :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 (3) Submit Documentation Feedback (3) 31 ...

  • Page 32

    ... For proper operation the enable pins must be terminated and must not be left floating. 32 Submit Documentation Feedback Product Folder Link(s) Figure t t Start RAMP Figure 31. Soft Start :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com has expired. Start 31. Copyright © 2011, Texas Instruments Incorporated ...

  • Page 33

    ... POWER_ON=HIGH will typically be asserted by the application processor to keep the PMU in ON-state after the power button at PB_IN is released. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732-Q1 /RESET + delay - Vref = RESET Figure 32. Reset Timing :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 Submit Documentation Feedback 33 ...

  • Page 34

    ... PB_IN=0 PB_IN=1 && POWER POWER_ON=1 OFF 3 SYS = ON POWER_ON=0 POWER POWER POWER_ON=1 ON_1 ON_2 SYS = ON SYS = ON Figure 33. State Machine :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com DCDC converters power down LDOs power down depending on sequencing option Copyright © 2011, Texas Instruments Incorporated ...

  • Page 35

    ... The A/D converter uses an internal 2.26V reference. The reference needs a bypass capacitor for stability which Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732-Q1 , exceeds typically 150°C for the DCDC converters or LDOs, the device J /Rset × K ISET ISET :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 ) Submit Documentation Feedback 35 ...

  • Page 36

    ... HiZ HiZ NMOS HiZ TSREF GND PMOS NMOS TSREF GND GND TGATE NMOS NMOS :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com TSX2 Table 2. The touch screen MODE MEASUREMENT X-Position Voltage TSY1 Y-Position Voltage TSX1 Pressure Current TSX1 and TSX2 Plate X Current TSX1 ...

  • Page 37

    ... TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732-Q1 Table 2. TSC Modes (continued) CONNECTIONS TSX2 TSY1 TSY2 A/D A/D A/D TGATE TGATE TGATE OPEN OPEN OPEN Disabled (no interrupt) :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 MODE MEASUREMENT A/D ADC used as stand alone ADC using its analog inputs None Table 3. Submit Documentation Feedback 37 ...

  • Page 38

    ... ADRESULT / 1024 pos – R //R – VTSREF/ [(V / 22k) × 150] ADC R // × X × (1 – pos pos R // × Y × (1 – pos pos :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com x2 y2 Copyright © 2011, Texas Instruments Incorporated ...

  • Page 39

    ... PRESSURE MEASUREMET Figure 36. Pressure Measurement TSY1 TSX1 TSX2 TSY2 Y PLATE RESISTANCE MEASUREMENT :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 TSY1 PMOS TSREF NMOS TSY2 Y POSITION MEASUREMENT TSY1 NMOS ...

  • Page 40

    ... R X2 TGATE TSX2 STANDBY MODE Figure 38. Touch Screen Standby Mode 2 C specifications, allowing transfers Data line Change stable; of data data valid allowed :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com TSY1 NMOS NMOS TSY2 Copyright © 2011, Texas Instruments Incorporated ...

  • Page 41

    ... R7 R0 ACK Register Slave Address Address Repeated Start ... .. .. .. R7 R0 ACK A6 0 Stop Start Register Slave Address Address :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 P STOP Condition ... ... ACK 0 0 Data Stop ... .. R/W ACK D7 D0 ACK 1 0 Slave Master Drives ...

  • Page 42

    ... STOP condition setup time su(STO) t Bus free time (BUF) 42 Submit Documentation Feedback Product Folder Link( (HIGH) t su(STA) t h(DATA) t su(DATA) STA Figure 44. Serial I/f Timing Diagram :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com t h(STA) t su(STO) STO MIN MAX UNIT 400 kHz 600 ns 1300 ns 300 ns ...

  • Page 43

    ... USB power AC power AC input enable enable current MSB Voltage UVLO UVLO removed UVLO AC OR UVLO R/W R/W R/W :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 input USB input USB input current LSB current MSB current LSB Voltage Voltage Voltage ...

  • Page 44

    ... Product Folder Link( MASK TSC INT PB_IN Cleared when Cleared when Cleared when Cleared when read UVLO UVLO R :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com USB or AC USB or AC PB_IN input voltage input voltage INT applied removed read ...

  • Page 45

    ... Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732- DPPM Thermal Term active Suspend Current UVLO UVLO UVLO :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 Chg Prechg BatTemp Timeout Timeout error UVLO UVLO UVLO ...

  • Page 46

    ... Bit will not reset the charger. Use CHARGER RESET Bit to reset charger. 46 Submit Documentation Feedback Product Folder Link( Safety timer SENSOR Charger enable TYPE UVLO UVLO UVLO UVLO R/W R/W R/W :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com Charge Suspend Charger Termination reset Charge enable ON/OFF UVLO UVLO UVLO R/W R/W R/W R/W Copyright © ...

  • Page 47

    ... Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732- Charge Charge voltage voltage voltage selection1 selection0 UVLO UVLO UVLO R/W R/W R/W :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 Submit Documentation Feedback ...

  • Page 48

    ... Product Folder Link( Power path Termination Precharge DPPM DPPM current time threshold0 factor1 UVLO UVLO UVLO R/W R/W R/W :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com Termination Charger Disable current active Isink at USB factor0 UVLO UVLO UVLO UVLO R/W R/W R Copyright © 2011, Texas Instruments Incorporated ...

  • Page 49

    ... TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 INPUT INPUT INPUT SELECT_2 SELECT_1 SELECT_0 UVLO UVLO UVLO R/W R/W R/W INPUT SELECTED Voltage at AD_IN1 Voltage at AD_IN2 Voltage at AD_IN3 Voltage at AD_IN4 Voltage at TS pin Voltage at ISET pin == battery charge ...

  • Page 50

    ... GND V2 V2 GND GND A/D A/D A/D A/D open open open open AD_BIT5 AD_BIT4 AD_BIT3 :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com TSC_M2 TSC_M1 TSC_M0 UVLO UVLO UVLO R R/W R/W MODE MEASUREMENT X-Position Voltage TSY1 Y-Position Voltage TSX1 Pressure Current TSX1 and ...

  • Page 51

    ... B5 B4 PGOOD PGOOD PGOOD PGOOD DELAY 0 VDCDC1 VDCDC2 PGOOD PGOOD VDCDC1 VDCDC2 PGOOD PGOOD VDCDC1 VDCDC2 R/W R/W R :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 AD_BIT9 AD_BIT8 MSB PGOOD PGOOD PGOOD VDCDC3 LDO1 ...

  • Page 52

    ... MASK MASK MASK VDCDC3 and VDCDC1 VDCDC2 LDO1 UVLO UVLO UVLO R R/W R/W :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com MASK MASK MASKLDO1 VDCDC3 LDO2 UVLO UVLO UVLO R/W R/W R/W Copyright © 2011, Texas Instruments Incorporated ...

  • Page 53

    ... TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732- DCDC1 DCDC_SQ1 DCDC_SQ0 ENABLE 1 See Table 9 See Table 9 1 DCDC1_E DCDC2_EN DCDC3_EN NZ UVLO UVLO UVLO R/W R/W R/W :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 DCDC2 DCDC3 LDO1 LDO2 ENABLE ENABLE ENABLE ENABLE LDO_ENZ LDO_ENZ ...

  • Page 54

    ... EN_DCDC3 PIN 54 Submit Documentation Feedback Product Folder Link(s) EN_DCDC2 PIN disabled disabled enabled CON_CTRL1<2> DCDC3 CONVERTER :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com CON_CTRL1<3> DCDC2 CONVERTER 0 x disabled 1 0 disabled 1 1 enabled disabled disabled enabled Copyright © 2011, Texas Instruments Incorporated ...

  • Page 55

    ... UVLO. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732- PWR_D DS_RDY MASK_EN_DCDC3 S UVLO UVLO UVLO R/W R/W R/W :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 UVLO UVLO1 UVLO0 hysteresis BG_GOOD BG_GOOD BG_GOOD R/W R/W R/W Submit Documentation Feedback 55 ...

  • Page 56

    ... FPWM FPWM DCDC1 DCDC2 DCDC2 DCDC1 discharge discharge UVLO UVLO UVLO R/W R/W R DCDC1[5] DCDC1[4] DCDC1[3] UVLO UVLO UVLO R R/W R/W :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com DCDC3 LDO1 discharge discharge discharge UVLO UVLO UVLO UVLO R/W R/W R DCDC1[2] DCDC1[1] DCDC1[0] UVLO UVLO UVLO ...

  • Page 57

    ... R R/W R/W R :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 DCDC2[2] DCDC2[1] DCDC2[0] UVLO UVLO UVLO R/W R/W R DCDC2[2] DCDC2[1] DCDC2[0] UVLO UVLO UVLO R/W R/W R DCDC3[2] DCDC3[1] DCDC3[0] UVLO ...

  • Page 58

    ... TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com ...

  • Page 59

    ... R R register DEFDCDC2_LOW, DEFDCDC2_HIGH, VDCDC3 1 0 SLEW RATE 0 0 0.11 mV/ 0.22 mV/ 0.45 mV/ 0.9 mV/ 1.8 mV/ 3.6 mV/ 7.2 mV/ Immediate :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 SLEW2 ...

  • Page 60

    ... LDO and a DCDC converter made sure they will ramp at the same time, given the fact the DCDC converters have an internal 170us delay as well. 60 Submit Documentation Feedback Product Folder Link( LDO_SQ0 LDO1[3] UVLO UVLO R/W R/W R :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com LDO1[2] LDO1[1] LDO1[0] UVLO UVLO UVLO UVLO R/W R/W R/W Copyright © ...

  • Page 61

    ... LDO2[5] LDO2[4] LDO2[3] UVLO UVLO R/W R/W R/W :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 LDO1 OUTPUT VOLTAGE 1.0 V 1.1 V 1.2 V 1.25 V 1.3 V 1.35 V 1.4 V 1.5 V 1.6 V 1.8 V 2.5 V 2.75 V 2.8 V 3.0 V 3 LDO2[2] LDO2[1] LDO2[0] UVLO UVLO UVLO ...

  • Page 62

    ... UVLO UVLO R R/W R LED DUTY LED DUTY LED DUTY CYCLE_5 CYCLE_4 CYCLE_3 UVLO UVLO UVLO R/W R/W R/W :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com LED DUTY LED DUTY LED DUTY CYCLE_2 CYCLE_1 CYCLE_0 UVLO UVLO ...

  • Page 63

    ... Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732-Q1 APPLICATION INFORMATION Table 4. Tested Inductors RECOMMENDED INDUCTOR VALUE MAXIMUM DC CURRENT 0.6 A 2.2 mH 1.2 A 2.2 mH 1.5 A 2.2 mH 1.5 A 2.2 mH :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 Equation 4. (4) (5) SUPPLIER Coilcraft Coilcraft Coilcraft TDK Submit Documentation Feedback 63 ...

  • Page 64

    ... Cout ´ ´ ¦ è ø Table 5. Possible Capacitors 0805 TDK C2012X5R0J226MT 0805 Taiyo Yuden JMK212BJ226MG 0805 Taiyo Yuden JMK212BJ106M 0805 TDK C2012X5R0J106M :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com (6) (7) Ceramic Ceramic Ceramic Ceramic Copyright © 2011, Texas Instruments Incorporated ...

  • Page 65

    ... Vsw — voltage drop at the internal NMOS switch I — average current in NMOS when turned on AVG Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732-Q1 (8) :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 (9) Submit Documentation Feedback (8) ( ...

  • Page 66

    ... H m Table 6. Tested Inductors INDUCTOR TYPE INDUCTOR VALUE LPS3015 18 mH LPS4018 47 mH LPS4018 47 mH :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com 140 mV = 117 mA Table 6 with the test conditions as SUPPLIER Coilcraft Coilcraft Coilcraft Copyright © 2011, Texas Instruments Incorporated (10) (11) (12) (13) ...

  • Page 67

    ... VALUE SIZE 4 1206 4 1210 Table 8. NTCs Supported CURVE / B VALUE RT2 NEEDED FOR LINEARIZATION Curve 2 / B=3477 Curve 1 / B=3964 :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 Table 7 for reference. CAPACITOR TYPE MANUFACTURER UMK316BJ475KL Taiyo Yuden GRM32ER71H475KA Murata MANUFACTURER 75k Several ...

  • Page 68

    ... Figure 46. Changing the Temperature Range 68 Submit Documentation Feedback Product Folder Link(s) RT1 TS 2.25 V RT2 V (45) HOT + - + V (0) COLD - Figure 45. Linearizing the NTC 46. RT1 RT3 TS 2.25 V RT2 V (45) HOT + - + V (0) COLD - :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com Table 8. NTC (18) NTC Copyright © 2011, Texas Instruments Incorporated ...

  • Page 69

    ... Product Folder Link(s) TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732-Q1 RNTC ( Temperature - (T) VTS ( Temperature - (T) Figure 48. Resulting TS Voltage :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 Figure 48 shows the result Submit Documentation Feedback 69 ...

  • Page 70

    ... L1, L2, L3 and L4 traces). See the EVM users guide for details about the layout for TPS6507x. 70 Submit Documentation Feedback Product Folder Link(s) Table 9. Sequencing Settings LDO_SQ[2..0] :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com Table 9 with COMMENT Copyright © 2011, Texas Instruments Incorporated ...

  • Page 71

    ... F m PGND BC847 PowerPad(TM) AGND PB_OUT PGOOD SDAT SCLK INT POWER_ON Reset delay Figure 49. Powering OMAP-L138 :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 OMAP-L138 RTC_CVDD (1.2V) USB0_VDDA33 (3.3 V) USB1_VDDA33 (3.3 V) Sense DVDD3318_A (3.3V or 1.8 V) DVDD3318_B (3.3V or 1.8 V) DVDD3318_C (3.3V or 1.8 V) CVDD (1.2 V) SATA_VDD (1.2 V) PLL0_VDDA (1.2 V) PLL1_VDDA (1.2 V) USBs CVDD (1.2 V) VDDARNWA/1 (1 ...

  • Page 72

    ... POWR_ON = HIGH asserted HIGH by the application processor any time while m 250 s m 250 s m 170 s m 400 ms Figure 50. Timing for OMAP-L138 :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com 50 ms debounce PB_IN = LOW to keep the system alive Copyright © 2011, Texas Instruments Incorporated ...

  • Page 73

    ... VIN SYS LDO EN_EXTLDO EN EN_wLED POWER_ON EN_DCDC3 PB_OUT PGOOD SDAT SCLK INT Figure 51. Powering Atlas IV :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 ALTAS IV VCC_3V3 (VDDIO) VCC_1V8 (VDDIO_MEM) VDD_PDN (1.2 V) VDD_PRE (1.2 V) VDDPLL (1.2 V) VDD_RTCIO GPIO (enable wLED) GPIO (power hold) X_PWR_EN VIO PB_INTERRUPT ...

  • Page 74

    ... Vout,nominal 0.95 x Vout,nominal 1ms 250 s m 1ms 250 s m 170 s 170 s 250 20ms Figure 52. Timing for Atlas IV :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com 15s 50ms debounce 250 0.5ms Copyright © 2011, Texas Instruments Incorporated ...

  • Page 75

    ... See timing diagrams for Sirf Prima SLEEP and DEEP SLEEP in Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732-Q1 Figure 53 and :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 Figure 54. Submit Documentation Feedback 75 ...

  • Page 76

    ... Bit MASK_EN_DCDC3 is cleared by the application processor. 170 s m DCDC3 and LDO1 are enabled / disabled by EN_DCDC3 to m 170 s 250 s m 170 s m 20ms :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com 15s enter / exit SLEEP mode 250 0.5ms Copyright © 2011, Texas Instruments Incorporated ...

  • Page 77

    ... DS_RDY=1, start wake-up sequence; otherwise start initial power-up from OFF state set Bits DS_RDY to indicate memory was backed-up set Bits PWR_DS to set Titan 2 to DEEP SLEEP mode 20ms :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 wakeup from DEEP SLEEP 0.95 x Vout,nominal ...

  • Page 78

    ... EN_DCDC1 SYS VDDS TPS3825-33DBVT EN_DCDC2 SYS VDD /RST /MR EN_DCDC3 GND PB_OUT POWER_ON PGOOD SDAT SCLK /INT /Reset :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com OMAP35xx VDDS_MMC1(1.8V / 3.0V) LDO VDDS_WKUP_BG (1.8V) VDDS_MEM; VDDS VDDS_SRAM VDDCORE (1.2V) VDD_MPU_IVA (1.2V) VDDA_DAC (1.8V) VDDS_DPLL_DLL (1.8V) VDDS_DPLL_PER (1.8V) VDDS SN74LVC1G06DCK VCC A SYS_OFF_MODE Y GND ...

  • Page 79

    ... TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732-Q1 can be released HIGH any time after POWR_ON=HIGH asserted HIGH by the application processor (OMAP) any time while /PB_IN=LOW to keep the system alive 250 s m 250 s m 250 s m 400ms :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 Submit Documentation Feedback 79 ...

  • Page 80

    ... SYS EN_DCDC1 EN_DCDC2 EN_DCDC3 PB_OUT POWER_ON PGOOD SDAT SCLK /INT AVDD6 BYPASS INT_LDO /Reset Figure 57. TPS650731 for OMAP35xx :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com OMAP35xx VDDS_WKUP_BG (1.8 V) VDDS_MEM; VDDS VDDS_SRAM VDDCORE (1.2 V) VDD_MPU_IVA (1.2 V) VDDA_DAC (1.8 V) VDDDLL VDDS_DPLL_DLL (1.8 V) VDDS_DPLL_PER (1.8 V) VIO GPIO (/disable power) SYS.nRESPWRON SDAT ...

  • Page 81

    ... HIGH any time after POWR_ON=HIGH 50ms debounce asserted HIGH by the application processor any time while /PB_IN=LOW to keep the system alive m 250 s m 250 s m 170 enabled by OMAP35xx by I2C command 400ms :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 Submit Documentation Feedback 81 ...

  • Page 82

    ... SYS EN_DCDC1 EN_DCDC2 EN_DCDC3 PB_OUT POWER_ON PGOOD SDAT SCLK /INT AVDD6 BYPASS SYS INT_LDO SYS /Reset :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 www.ti.com AM3505 VDDS1-5 (1.8V) VDDSHV (3.3V) VDD_CORE (1.2V) VDDS_DPLL (1.8V) VDDA1P8V(1.8V) GPIO (/disable power) SYS.nRESPWRON SDAT SCLK /INT TPS79918 Vin VDDS_SRAM (1.8V) LDO EN ...

  • Page 83

    ... TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732-Q1 can be released HIGH any time after POWR_ON=HIGH 50ms debounce asserted HIGH by the application processor any time while /PB_IN=LOW to keep the system alive 250us 250us 170us 400ms :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 SLVSAP7 – JANUARY 2011 Submit Documentation Feedback 83 ...

  • Page 84

    PACKAGING INFORMATION Orderable Device (1) Package Type Package Status TPS650732TRSLRQ1 ACTIVE VQFN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and ...

  • Page 85

    TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing TPS650732TRSLRQ1 VQFN RSL PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 48 2500 330.0 16.4 6.3 Pack Materials-Page 1 14-Jul-2012 ...

  • Page 86

    Device Package Type TPS650732TRSLRQ1 VQFN PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) RSL 48 2500 Pack Materials-Page 2 14-Jul-2012 Width (mm) Height (mm) 367.0 367.0 38.0 ...

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    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest ...