TPS65070_09

Manufacturer Part NumberTPS65070_09
DescriptionSingle Chip Power Solution for Battery Powered Systems
ManufacturerTI [Texas Instruments]
TPS65070_09 datasheet
 


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Single Chip Power Solution for Battery Powered Systems
Check for Samples: TPS65070, TPS65072, TPS65073,
FEATURES
1
Charger/Power Path Management:
2
– 2A Output Current on the Power Path
– Linear Charger; 1.5A Maximum Charge
Current
– 100mA/500mA/ 800mA/1300mA Current
Limit From USB Input
– Thermal Regulation, Safety Timers
– Temperature Sense Input
3 Step-Down Converters:
– 2.25MHz Fixed Frequency Operation
– Up to 1.5A of Output Current
– Adjustable or Fixed Output Voltage
– V
Range From 2.8V to 6.3V
IN
– Power Save Mode at Light Load Current
– Output Voltage Accuracy in PWM Mode
±1.5%
– Typical 19 μA Quiescent per Converter
– 100% Duty Cycle for Lowest Dropout
LDOs:
– Fixed Output Voltage
– Dynamic Voltage Scaling on LDO2
– 20μA Quiescent Current
– 200mA Maximum Output Current
– V
Range From 1.8V to 6.3V
IN
wLED Boost Converter:
– Internal Dimming Using I2C
– Up to 2 × 10 LEDs
– Up to 25mA per String With Internal Current
Sink
2
I
C Interface
10 Bit A/D Converter
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OMAP, PowerPAD are trademarks of Texas Instruments.
2
UNLESS
OTHERWISE
NOTED
this
document
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Touch Screen Interface
Undervoltage Lockout and Battery Fault
Comparator
APPLICATIONS
Portable Navigation Systems
PDAs, Pocket PCs
OMAP™ and Low Power DSP Supply
DESCRIPTION
The TPS6507x are single chip Power Management
ICs for portable applications consisting of a battery
charger with power path management for a single
Li-Ion or Li-Polymer cell. The charger can either be
supplied by a USB port on pin USB or by a dc voltage
from a wall adapter connected to pin AC. Three
highly efficient 2.25MHz step-down converters are
targeted at providing the core voltage, memory and
I/O voltage in a processor based system. The
step-down converters enter a low power mode at light
load for maximum efficiency across the widest
possible range of load currents. For low noise
applications the devices can be forced into fixed
frequency PWM using the I
step-down converters allow the use of small inductors
and capacitors to achieve a small solution size. The
TPS6507x also integrate two general purpose LDOs
for an output current of 200mA. These LDOs can be
used to power an SD-card interface and an
always-on rail, but can be used for other purposes as
well. Each LDO operates with an input voltage range
between 1.8V and 6.3V allowing them to be supplied
from one of the step-down converters or directly from
the main battery. An inductive boost converter with
two programmable current sinks power two strings of
white LEDs.
The TPS6507x come in a 48-pin leadless package
(6mm × 6mm QFN) with a 0,4mm pitch.
contains
TPS65070, TPS65072, TPS65073
TPS650731, TPS650732
SLVS950B – JULY 2009 – REVISED DECEMBER 2009
TPS650731, TPS650732
2
C interface. The
Copyright © 2009, Texas Instruments Incorporated

TPS65070_09 Summary of contents

  • Page 1

    Single Chip Power Solution for Battery Powered Systems Check for Samples: TPS65070, TPS65072, TPS65073, FEATURES 1 • Charger/Power Path Management: 2 – 2A Output Current on the Power Path – Linear Charger; 1.5A Maximum Charge Current – 100mA/500mA/ 800mA/1300mA ...

  • Page 2

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation ...

  • Page 3

    RECOMMENDED OPERATING CONDITIONS BATTERY CHARGER AND POWER PATH V Input voltage for power path manager at pins AC or USB IN Input voltage for power path manager at pins AC or USB, charger and power path active (no overvoltage ...

  • Page 4

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS VSYS = 3.6V, EN_DCDCx = VSYS 2.2μH, C otherwise noted) PARAMETER SUPPLY CURRENT V Input voltage range for DCDC converters INDCDC Operating quiescent ...

  • Page 5

    DCDC1 CONVERTER PARAMETER V Input voltage range VINDCDC1 I Maximum output O R High side MOSFET on-resistance DS(ON) I High side MOSFET leakage current LH R Low side MOSFET on-resistance DS(ON) I Low side MOSFET leakage current LL I ...

  • Page 6

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 DCDC2 CONVERTER (continued) PARAMETER Default output voltage for TPS65070, TPS650732 Vout Default output voltage for TPS65072 Default output voltage for TPS65073, TPS650731 DC output voltage accuracy; PFM ...

  • Page 7

    DCDC3 CONVERTER (continued) PARAMETER Fixed output voltage range Default output voltage for TPS65070 Default output voltage for TPS65072 V out Default output voltage for TPS65073, TPS650731, TPS650732 DC output voltage accuracy; PFM mode DC output voltage accuracy; PWM mode ...

  • Page 8

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 VLDO1 and VLDO2 LOW DROPOUT REGULATORS PARAMETER V Input voltage range for LDO1, LDO2 INLDO V LDO1 output voltage range LDO1 V LDO2 output voltage range LDO2 ...

  • Page 9

    BOOST CONVERTER PARAMETER V voltage at L4 pin L4 Vsink1,2 Input voltage at ISINK1, ISINK2 pins V Internal overvoltage protection OUT Maximum boost factor (Vout/Vin) T Minimum off pulse width min_off R N-channel MOSFET on-resistance DS(ON) N-channel MOSFET ...

  • Page 10

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 ADC CONVERTER PARAMETER Input voltage range at AD_IN1 to AD_IN4 pin (channel 0 to channel 3) V Input voltage range internal channel 6 to channel 9 IN ...

  • Page 11

    POWER PATH (continued) PARAMETER T Power detected deglitch DGL(DT) VIN Input over voltage detection threshold (OVP) POWER PATH TIMING T Switching from AC to BAT SW(ACBAT Switching from USB to BAT W(USBBAT) T Switching from USB to ...

  • Page 12

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 BATTERY CHARGER PARAMETER CHARGER SECTION Battery discharge current V Battery charger voltage o(BATREG) V Pre-charge to fast-charge transition threshold LOWV Deglitch time on pre-charge to fast-charge t ...

  • Page 13

    BATTERY CHARGER (continued) PARAMETER THERMAL REGULATION T Temperature regulation limit J(REG) T Charger thermal shutdown J(OFF) T Charger thermal shutdown hysteresis J(OFF-HYS) PIN ASSIGNMENT (TOP VIEW) TPS65072 AVDD6 1 VLDO2 2 VINLDO1/2 3 VLDO1 4 BAT 5 BAT 6 ...

  • Page 14

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 PIN I/O NAME NO. Analog input1 for A/D converter TPS65070, TPS65073, TPS650731, TPS650732 only: AD_IN1 43 I (TSX1) Input 1 to the x-plate for the touch screen. ...

  • Page 15

    PIN I/O NAME NO. Power_ON input for the internal state machine. After PB_IN was pulled LOW to turn on the TPS6507x, the POWER_ON pin needs to be pulled HIGH by the application processor to keep the system in ON-state ...

  • Page 16

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 AC USB Iset TSX1 TSX2 AD_IN1 Touch screen AD_IN2 biasing AD_IN3 AD_IN4 TSY1 TSY2 INT PB_IN VIN_DCDC1/2 EN_DCDC1 DEFDCDC2 EN_DCDC2 VIN_DCDC3 DEFDCDC3 EN_DCDC3 Sequencing VINLDO1/2 EN_LDO1(I2C) EN_LDO2(I2C) ...

  • Page 17

    PARAMETER MEASUREMENT INFORMATION The data sheet graphs were taken on the TPS6507x evaluation module (EVM). Please refer to the EVM user´s guide (SLVU291) for the setup information. TABLE OF GRAPHS Efficiency DCDC1 vs Load current / PWM mode Efficiency ...

  • Page 18

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 EFFICIENCY DCDC1 vs LOAD CURRENT/PWM MODE 100 PWM Mode 25°C 80 3. ...

  • Page 19

    EFFICIENCY DCDC2 vs LOAD CURRENT/PWM MODE 100 PWM Mode 25° 3. 0.0001 0.001 0.01 0 Output Current - A ...

  • Page 20

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 EFFICIENCY DCDC3 vs LOAD CURRENT/PWM MODE 100 PWM Mode 25° 3. 4. ...

  • Page 21

    LOAD TRANSIENT RESPONSE CONVERTER 3 V DCDC3 (Offset: 1.2 V) OUT I DCDC3 Load V DCDC3 = 3 Load = 150 mA - 1350 mA - 150 mA Figure 13. LINE TRANSIENT RESPONSE CONVERTER 2 V DCDC2 ...

  • Page 22

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 OUTPUT VOLTAGE RIPPLE AND INDUCTOR CURRENT CONVERTER 2 – PWM MODE V DCDC2 (Offset: 1.78 V) OUT I DCDC2 3 Load = ...

  • Page 23

    LINE TRANSIENT RESPONSE LDO1 bat V LDO1 LOAD = LDO1 (Offset: 1.8 V) OUT V LDO1 (Offset Figure 21. wLED ...

  • Page 24

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 BATTERY CHARGER AND POWER PATH he TPS6507x integrate a Li-ion linear charger and system power path management targeted at space-limited portable applications. The TPS6507x power the system ...

  • Page 25

    POWER DOWN The charger remains in a power down mode when the input voltage at the AC or USB pin is below the under-voltage lockout threshold V UVLO not interpreted. POWER-ON RESET The charger resets when the input voltage ...

  • Page 26

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 PRECHARGE V BAT(REG) I O(CHG) V LOWV I (PRECHG) I (TERM) In the pre-charge phase, the battery is charged at a current of I battery voltage crosses ...

  • Page 27

    If the BAT pin voltage falls below V removed. The device then checks for battery insertion: it turns on FET Q2 and sources I pin for duration the voltage does not rise above V DET new ...

  • Page 28

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 PRECHARGE V O(REG) I O(CHG) Battery Voltage V (LOWV) I (PRECHG) I (TERM) T J(REG) Timer Fault: The following events generate a fault status the ...

  • Page 29

    Sensor type 10K curve 2 100k curve 1 BATTERY CHARGER STATE DIAGRAM TEMP_ERROR=0. Also register should be enabled. NO EN_DCH=1 && DBATSINK = 1 for Tdet Then release. EN_DCH returns to previous state. DCDC CONVERTERS AND LDOs OPERATION The ...

  • Page 30

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 During PWM operation the converter use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the ...

  • Page 31

    POWER SAVE MODE The Power Save Mode is enabled by default. If the load current decreases, the converter will enter Power Save Mode operation automatically. During Power Save Mode the converter skips switching and operates with reduced frequency in ...

  • Page 32

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 100% Duty Cycle Low Dropout Operation The device starts to enter 100% duty cycle Mode once the input voltage comes close the nominal output voltage. In order ...

  • Page 33

    ENABLE To start up each converter independently, the device has a separate enable pin for each of the DCDC converters. In order to enable any converter with its enable pins, the TPS6507x devices need ON-state by ...

  • Page 34

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 PB_IN (Push-button IN) This pin is the ON/OFF button for the PMU to leave OFF-state and enter ON-state by pulling this pin to GND. Entering ON-state will ...

  • Page 35

    PB_OUT This pin is a status output. PB_OUT is used as the wake-up interrupt to an application processor based on the status of PB_IN. If PB_IN=LOW, PB_OUT = LOW (after 50ms debounce). If PB_IN=HIGH, PB_OUT= high impedance (HIGH). The ...

  • Page 36

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 internal current sink at pins Isink1 and Isink2. The maximum current through the current sinks is set with two external resistors connected from pins ISET1 and ISET2 ...

  • Page 37

    The touch screen interface consists of a digital state machine, a voltage reference, and an analog switch matrix which is connected to the four wire resistive touch screen inputs (TSX1, TSX2, TSY1, TSY2) and an internal 10-Bit ADC. The ...

  • Page 38

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 MEASUREMENT CHANNEL X Plate resistance AD_IN14 Y plate resistance AD_IN14 X position AD_IN14 Y position AD_IN14 Pressure AD_IN14 Performing Measurements Using the Touch Screen Controller In order ...

  • Page 39

    TSX1 PMOS TSREF R X2 NMOS TSX2 X POSITION MEASUREMENT TO ADC TGATE 22 kW TSX1 I L PMOS I L/150 TGATE TSREF TO ADC TGATE 22 kW NMOS TSX2 X PLATE RESISTANCE MEASUREMENT Figure ...

  • Page 40

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 TO INT BLOCK TSREF I2C Interface Specification: Serial interface The serial interface is compatible with the standard and fast mode I 400kHz. The interface adds flexibility to ...

  • Page 41

    DATA CLK S START Condition SCLK ... SDAT ... Start Slave Address NOTE: SLAVE=TPS6507x SCLK ... SDAT .. A6 A0 R/W ACK 0 0 Start Slave Address NOTE: SLAVE=TPS6507x Figure 42. Serial I/f READ from ...

  • Page 42

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 DATA t( BUF) t (LOW) CLK t h(STA) STO STA f Clock frequency MAX t Clock high time wH(HIGH) t Clock low time wL(LOW) t SDAT and ...

  • Page 43

    REGISTERS PPATH1. Register Address: 01h PPATH1 B7 B6 Bit name and USB power AC power function Default x x Set by signal Default value loaded by: Read/write R R Bit 7 USB power USB power is not ...

  • Page 44

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 INT. Register Address: 02h INT B7 B6 MASK Bit name and MASK TSC function AC/USB Default 0 0 Set by signal Default value UVLO UVLO loaded by: ...

  • Page 45

    CHGCONFIG0. Register Address: 03h CHGCONFIG0 B7 Thermal Bit name and function regulation Default x Set by signal Default value loaded by: UVLO Read/write R Bit 7 THERMAL REGULATION charger is in normal operation 1 = charge current ...

  • Page 46

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 CHGCONFIG1. Register Address: 04h CHGCONFIG1 B7 Charge safety Charge safety Bit name and function timer value1 Default 0 Set by signal Default value loaded UVLO by: Read/write ...

  • Page 47

    CHGCONFIG2. Register Address: 05h CHGCONFIG2 B7 Dynamic Precharge Bit name and function Timer function Default 1 Set by signal Default value loaded by: UVLO Read/write R/W Bit 7 DYNAMIC TIMER FUNCTION 0 = safety timers run with their nominal ...

  • Page 48

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 CHGCONFIG3. Register Address: 06h CHGCONFIG3 B7 Power path Disable Bit name and function Isink at AC threshold1 Default 0 Set by signal Default value loaded by: UVLO ...

  • Page 49

    ADCONFIG. Register Address: 07h ADCONFIG B7 Conversion Bit name and function AD enable Default 0 Set by signal Default value loaded by: UVLO Read/write R/W Bit 7 AD ENABLE A/D converter disabled 1 = A/D converter enabled ...

  • Page 50

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 TSCMODE. Register Address: 08h TSCMODE B7 Bit name and function Default 0 Set by signal Default value loaded by: Read/write R Bit 3..0 MODE SELECT BITS FOR ...

  • Page 51

    ADRESULT_2. Register Address: 0Ah ADRESULT_2 B7 Bit name and function Default 0 Set by signal Default value loaded by: R Read/write PGOOD. Register Address: 0Bh PGOOD B7 Bit name and function Reset Default –70 x –73, –731, –732 –72 ...

  • Page 52

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 PGOODMASK. Register Address: 0Ch B7 Bit name and function Default –70, –72 0 –73, –731, –732 Set by signal Default value loaded by: Read/write R Bit 5 ...

  • Page 53

    CON_CTRL1. Register Address: 0Dh CON_CTRL1 B7 Bit name and function DCDC_SQ2 Default –70, –72, -73, -732 See Table 9 for TPS65731 only Set by signal Default value loaded by: UVLO Read/write R/W The CON_CTRL1 register can be used to ...

  • Page 54

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 Bit 4..0 DCDC1,2,3: See tables below EN_DCDC1 PIN CON_CTRL1<4> DCDC1 CONVERTER EN_DCDC3 PIN 54 Submit Documentation Feedback Product Folder Link(s): EN_DCDC2 ...

  • Page 55

    CON_CTRL2. Register Address: 0Eh CON_CTRL2 B7 ENABLE ENABLE Bit name and function 1s timer 5s timer Default 0 Set by signal Default value loaded UVLO UVLO by: Read/write R/W Bit 7…6 ENABLE TIMERS the state machine timers ...

  • Page 56

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 CON_CTRL3. Register Address: 0Fh CON_CTRL3 B7 FPWM Bit name and function DCDC3 Default 1 Default value loaded by: UVLO Read/write R/W Bit 7 FPWM DCDC3 ...

  • Page 57

    DEFDCDC2_LOW. Register Address: 11h DEFDCDC2_LOW B7 Bit name and function Default –70, –72, –732 0 –73, –731 Default value loaded by: Read/write R DEFDCDC2_HIGH. Register Address: 12h DEFDCDC2_HIGH B7 Bit name and function DCDC2 extadj Default –70, –732 –72 ...

  • Page 58

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 OUTPUT VOLTAGE [V] 0.725 0.750 0.775 0.800 0.825 0.850 0.875 0.900 0.925 0.950 0.975 1.000 1.025 1.050 1.075 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 ...

  • Page 59

    OUTPUT VOLTAGE [V] 2.350 2.400 2.450 2.500 2.550 2.600 2.650 2.700 2.750 2.800 2.850 2.900 3.000 3.100 3.200 3.300 DEFSLEW. Register Address: 15h DEFSLEW B7 Bit name and function Default 0 Default value loaded by: Read/write R The DEFSLEW ...

  • Page 60

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 LDO_CTRL1. Register Address: 16h LDO_CTRL1 B7 Bit name and function LDO_SQ2 LDO_SQ1 Default –70 –73, –731, –732, See Table 9 See –72 Default value loaded by: UVLO ...

  • Page 61

    Bit 3..0 LDO1(3) to LDO1(0): The Bits define the default output voltage of LDO1 according to the table below: LDO1[ DEFLDO2. Register Address: ...

  • Page 62

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 WLED_CTRL1. Register Address: 18h WLED_CTRL1 B7 Enable Bit name and function ISINK Default 0 Default value loaded by: UVLO Read/write R/W Bit 7 ENABLE ISINK ...

  • Page 63

    STEP-DOWN CONVERTERS OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR) Inductor Selection The step-down converters operate typically with 2.2μH output inductor. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. ...

  • Page 64

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 Vout 1 - Vin I = Vout ´ RMSCout L ´ ¦ At nominal load current the inductive converters operate in PWM mode and the overall output ...

  • Page 65

    ISET1 to GND. Dimming is done with an internal PWM modulator by changing the duty cycle in the current sinks from 1% to 100%. In order to set a LED current of less than 1% of the current defined ...

  • Page 66

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 The duty cycle for a boost converter is ¦ - Vin ¦ - Vsw With: Vsw = Rds I ...

  • Page 67

    Other inductors, with lower or higher inductance values can be used. A higher inductance will cause a lower inductor current ripple and therefore will provide higher efficiency. The boost converter will also stay in continuous conduction mode over a ...

  • Page 68

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 For best performance, the NTC needs to be linearized by connecting a resistor (RT2) in parallel to the NTC as shown in Figure 46. The resistor value ...

  • Page 69

    Figure 47. NTC [R(T)] and NTC in Parallel to RT2 [Rges(T)] 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 0.9 0.8 As Figure 47 shows, the result is an ...

  • Page 70

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 POWER SOLUTIONS FOR DIFFERENT APPLICATION PROCESSORS Default Settings For proper power supply design with TPS6507x, not only the default output voltage is relevant but also in what ...

  • Page 71

    Starting TPS6507x TPS6507x was developed for battery powered applications with focus on lowest shutdown and quiescent current. In order to achieve this, in shutdown all mayor blocks and the system voltage at the output of the power path (SYS) ...

  • Page 72

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 APPLICATION CIRCUITS TPS65070 charger / power USB ISET set charge current SYS sets default DEFDCDC2 voltage of DCDC2 to 1.8 ...

  • Page 73

    PB_IN PB_OUT level not defined as voltage at pull-up has not ramped at that time 50ms debounce SYS POWER_ON external LDO (RTC_CVDD) 1.2 V VDCDC3 (CVDD) 1.2 V 170 s 250 s m VLDO2 (SATA_VDD) 1.2 V VDCDC2 (VDDSHV) ...

  • Page 74

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 TPS65072 charger / power path USB ISET set charge current DEFDCDC2 DEFDCDC3 VINLDO1/2 SYS INT_LDO 2.2 F ...

  • Page 75

    PB_IN PB_OUT level not defined as voltage at pull-up has not ramped at that time 50ms debounce SYS POWER_ON EN_EXTLDO (VDD_RTCIO) 1ms VLDO2 (VDD_PRE) 1ms VDCDC1 (VCC_3V3) VDCDC2 (VCC_1V8) EN_DCDC3 (X_PWR_EN) VDCDC3 (VDD_PDN) VLDO1 (VDDPLL) PGOOD (X_RESET_B) Copyright © ...

  • Page 76

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 Prima SLEEP Mode and DEEP SLEEP Mode Support TPS6507x contains a sequencing option for the Sirf Prima processor. The sequencing option defines how the voltages are ramped ...

  • Page 77

    PB_IN PB_OUT level not defined as voltage at pull-up has not ramped at that time 50ms debounce SYS POWER_ON EN_EXTLDO (VDD_RTCIO) 1ms VLDO2 (VDD_PRE) VDCDC1 (VCC_3V3) VDCDC2 (VCC_1V8) Bit MASK_EN_DCDC3 EN_DCDC3 (X_PWR_EN) VDCDC3 (VDD_PDN) Bit MASK_EN_DCDC3 is set per ...

  • Page 78

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 PB_IN startup from OFF state PB_OUT level not defined as voltage at pull-up has not ramped at that time 50ms debounce SYS POWER_ON EN_EXTLDO (VDD_RTCIO) 1ms VLDO2 ...

  • Page 79

    TPS65073 AC 1uF USB charger / power path 1uF ISET set charge current DEFDCDC2 DEFDCDC3 VINLDO1/2 SYS 1uF /PB_IN ON / OFF AVDD6 AD_IN1 (TSX1) AD_IN2 (TSX2) AD_IN3 (TSY1) AD_IN4 (TSY2) BYPASS INT_LDO L4 SYS FB_wLED 1uF ISINK1 wLED ...

  • Page 80

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 PB_IN PB_OUT level not defined as voltage at pull-up has not ramped at that time 50ms debounce SYS POWER_ON VDCDC1 (VDDS_WKUP_BG, VDDS, VDDS_MEM ) 170 s + ...

  • Page 81

    TPS650731 charger / power path USB ISET set charge current DEFDCDC2 DEFDCDC3 VINLDO1/2 SYS 1uF PB_IN ON / OFF AD_IN1 (TSX1) AD_IN2 (TSX2) AD_IN3 (TSY1) AD_IN4 (TSY2) L4 SYS FB_wLED 1 F ...

  • Page 82

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 PB_IN PB_OUT level not defined as voltage at pull-up has not ramped at that time 50ms debounce SYS POWER_ON VDCDC1 (VDDS_WKUP_BG, VDDS, VDDS_MEM ) 170 s m ...

  • Page 83

    TPS650732 AC 1uF charger / power path USB 1uF ISET set charge current DEFDCDC2 SYS DEFDCDC3 VINLDO1/2 SYS 1uF /PB_IN ON / OFF AD_IN1 (TSX1) AD_IN2 (TSX2) AD_IN3 (TSY1) AD_IN4 (TSY2) L4 SYS FB_wLED 1uF ISINK1 wLED boost ISINK2 ...

  • Page 84

    TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 SLVS950B – JULY 2009 – REVISED DECEMBER 2009 /PB_IN PB_OUT level not defined as voltage at pull-up has not ramped at that time 50ms debounce SYS POWER_ON VDCDC1 (VDDS1-5 ) 1.8V 170us 250us VDCDC2 (VDDSHV) ...

  • Page 85

    Changes from Revision A (July) to Revision B • Changed title from ".....Navigation Systems" to ".......Battery Powered Systems" ................................................................ • Changed status of TPS65072RSL device to Production Data ............................................................................................. • Changed V Parameter from: "Fixed output voltage; PFM mode" ...

  • Page 86

    PACKAGING INFORMATION (1) Orderable Device Status TPS65070RSLR ACTIVE TPS65070RSLT ACTIVE TPS65072RSLR ACTIVE TPS65072RSLT ACTIVE TPS650731RSLR ACTIVE TPS650731RSLT ACTIVE TPS650732RSLR ACTIVE TPS650732RSLT ACTIVE TPS65073RSLR ACTIVE TPS65073RSLT ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended ...

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    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the ...