74ABT646APW NXP [NXP Semiconductors], 74ABT646APW Datasheet

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74ABT646APW

Manufacturer Part Number
74ABT646APW
Description
Octal bus transceiver/register; 3-state
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1. General description
2. Features and benefits
The 74ABT646A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT646A transceiver/register consists of bus transceiver circuits with 3-state
outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of
data directly from the input bus or the internal registers. Data on the A bus or B bus will be
clocked into the registers as the appropriate clock pin (CPAB or CPBA) goes HIGH.
Output Enable (OE) and Direction (DIR) pins are provided to control the transceiver
function. In the transceiver mode, data present at the high-impedance port may be stored
in either the A or B register or both.
The Select (SAB, SBA) pins determine whether data is stored or transferred through the
device in real-time. The DIR pin determines which bus receives data when OE is active
(LOW). In isolation mode (OE = HIGH), data from bus A may be stored in the B register
and/or data from bus B may be stored in the A register. When an output function is
disabled, the input function is still enabled and may be used to store and transmit data.
Only one of the two buses, A or B, may be driven at a time. The examples in
“Real time bus transfer and storage” on page 6
management functions that can be performed with the 74ABT646A.
I
I
I
I
I
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74ABT646A
Octal bus transceiver/register; 3-state
Rev. 03 — 15 March 2010
Combines 74ABT245 and 74ABT373A type functions in one device
Independent registers for A and B buses
Multiplexed real-time and stored data
Live insertion and extraction permitted
Output capability: +64 mA to 32 mA
Power-up 3-state
Power-up reset
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
N
N
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
demonstrate the four fundamental bus
Product data sheet
Figure 5

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74ABT646APW Summary of contents

Page 1

Octal bus transceiver/register; 3-state Rev. 03 — 15 March 2010 1. General description The 74ABT646A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT646A transceiver/register consists of bus transceiver ...

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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74ABT646AD +85 C 74ABT646ADB +85 C 74ABT646APW + Functional diagram CPAB 2 SAB 3 DIR 23 CPBA 22 SBA Fig 1 ...

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NXP Semiconductors DIR 23 CPBA 22 SBA 1 CPAB 2 SAB Fig 3. Logic diagram 74ABT646A_3 Product data sheet 1 of ...

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NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 4. Pin configuration 5.2 Pin description Table 2. Pin description Symbol CPAB SAB DIR A0, A1, A2, A3, A4, A5, A6, A7 GND B0, B1, B2, B3, B4, B5, B6 ...

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NXP Semiconductors 6. Functional description [1] Table 3. Function table Inputs OE DIR CPAB ...

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REAL TIME BUS TRANSFER REAL TIME BUS TRANSFER BUS B TO BUS DIR CPAB CPBA SAB SBA OE DIR Fig 5. Real time bus transfer and storage STORAGE ...

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NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input voltage I V output voltage O I input clamping current IK I output ...

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NXP Semiconductors 9. Static characteristics Table 6. Static characteristics Symbol Parameter V input clamping voltage IK V HIGH-level output OH voltage V LOW-level output voltage power-up LOW-level OL(pu) output voltage I input leakage current I I power-off ...

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NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure Symbol Parameter f maximum frequency see max t LOW to HIGH PLH propagation delay t HIGH to LOW PHL propagation delay t ...

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NXP Semiconductors 11. Waveforms and V are typical voltage output levels that occur with the output load Fig 6. Propagation delay clock input to output and clock pulse width, maximum clock frequency ...

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NXP Semiconductors OE, DIR 1 and V are typical voltage output levels that occur with the output load Fig 9. 3-state output enable time to LOW-level and output disable time ...

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NXP Semiconductors negative V M pulse positive V M pulse Input pulse definition Test data is given ...

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NXP Semiconductors 12. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...

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NXP Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. ...

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NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm ...

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NXP Semiconductors 13. Abbreviations Table 9. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 10. Revision history Document ID Release date 74ABT646A_3 ...

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NXP Semiconductors 15. Legal information 15.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

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NXP Semiconductors 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74ABT646A_3 Product data sheet http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 03 — 15 ...

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NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefi ...

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