74ACT374_01 STMICROELECTRONICS [STMicroelectronics], 74ACT374_01 Datasheet

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74ACT374_01

Manufacturer Part Number
74ACT374_01
Description
OCTAL D-TYPE FLIP-FLOP WITH 3 STATE OUTPUTS (NON INVERTED)
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
DESCRIPTION
The 74ACT374 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP-FLOP with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
These 8 bit D-Type Flip-Flop are controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to the logic that were setup at
the D inputs.
While the (OE) input is low, the 8 outputs will be in
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
HIGH SPEED:
f
LOW POWER DISSIPATION:
I
COMPATIBLE WITH TTL OUTPUTS
V
50 TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374
IMPROVED LATCH-UP IMMUNITY
MAX
CC
PLH
OH
IH
CC
= 4 A(MAX.) at T
= 2V (MIN.), V
| = I
(OPR) = 4.5V to 5.5V
2
= 260MHz (TYP.) at V
MOS technology.
t
PHL
OL
= 24mA (MIN)
IL
= 0.8V (MAX.)
A
=25°C
WITH 3 STATE OUTPUTS (NON INVERTED)
CC
= 5V
ORDER CODES
a normal logic state (high or low logic level); when
the OE is
impedance state.
The output control does not affect the internal
operation of flip-flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
OCTAL D-TYPE FLIP-FLOP
PACKAGE
TSSOP
SOP
DIP
DIP
high the outputs go to the high
74ACT374M
74ACT374B
TUBE
SOP
74ACT374
74ACT374MTR
74ACT374TTR
TSSOP
T & R
1/11

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74ACT374_01 Summary of contents

Page 1

WITH 3 STATE OUTPUTS (NON INVERTED) HIGH SPEED 260MHz (TYP MAX LOW POWER DISSIPATION A(MAX =25° COMPATIBLE WITH TTL OUTPUTS (MIN.), V = 0.8V (MAX.) IH ...

Page 2

INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE Don’t Care Z : High Impedance LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/11 PIN DESCRIPTION PIN No 1 ...

Page 3

ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current ...

Page 4

DC SPECIFICATIONS Symbol Parameter V V High Level Input IH Voltage V Low Level Input IL Voltage V High Level Output OH Voltage V Low Level Output OL Voltage I Input Leakage Cur- I rent I High Impedance OZ ...

Page 5

CAPACITIVE CHARACTERISTICS Symbol Parameter V C Input Capacitance IN Output C OUT Capacitance C Power Dissipation PD Capacitance (note defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current ...

Page 6

WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) 6/11 ...

Page 7

WAVEFORM 3: PULSE WIDTH (f=1MHz; 50% duty cycle) 74ACT374 7/11 ...

Page 8

Plastic DIP-20 (0.25) MECHANICAL DATA DIM. MIN. a1 0.254 B 1. 8/11 mm TYP. MAX. MIN. 0.010 1.65 0.055 0.45 0.25 25.4 8.5 2.54 22.86 7.1 3.93 3.3 1.34 ...

Page 9

SO-20 MECHANICAL DATA mm DIM. MIN. TYP 0. 0.35 b1 0. 12.60 E 10.00 e 1.27 e3 11.43 F 7. inch MAX. MIN. TYP. 2.65 0.20 0.004 2.45 ...

Page 10

DIM. MIN 0.05 A2 0.85 b 0.19 c 0.09 D 6.4 E 6. PIN 1 IDENTIFICATION 1 10/11 TSSOP20 MECHANICAL DATA mm TYP. MAX. 1.1 ...

Page 11

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. ...

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