74AVC8T245BQ NXP [NXP Semiconductors], 74AVC8T245BQ Datasheet

74AVC8T245BQ

Manufacturer Part Number

74AVC8T245BQ

Description

8-bit dual supply translating transceiver with configurable voltage translation; 3-state

Manufacturer

NXP [NXP Semiconductors]

Datasheet

1.74AVC8T245BQ.pdf (23 pages)

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1. General description

2. Features

The 74AVC8T245 is an 8-bit, dual supply transceiver that enables bidirectional level

translation. It features two data input-output ports (An and Bn), a direction control input

(DIR), a output enable input (OE) and dual supply pins (V

and V

suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V,

2.5 V and 3.3 V). Pins An, OE and DIR are referenced to V

referenced to V

DIR allows transmission from Bn to An. The output enable input (OE) can be used to

disable the outputs so the buses are effectively isolated.

The device is fully speciﬁed for partial power-down applications using I

circuitry disables the output, preventing any damaging backﬂow current through the

device when it is powered down. In suspend mode when either V

GND level, both An and Bn are in the high-impedance OFF-state.

74AVC8T245

8-bit dual supply translating transceiver with conﬁgurable

voltage translation; 3-state

Rev. 02 — 28 April 2009

Wide supply voltage range:

Complies with JEDEC standards:

ESD protection:

Maximum data rates:

CC(B)

JESD8-12 (0.8 V to 1.3 V)

JESD8-11 (0.9 V to 1.65 V)

JESD8-7 (1.2 V to 1.95 V)

JESD8-5 (1.8 V to 2.7 V)

JESD8-B (2.7 V to 3.6 V)

HBM JESD22-A114E Class 3B exceeds 8000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101C exceeds 1000 V

380 Mbit/s ( 1.8 V to 3.3 V translation)

260 Mbit/s ( 1.1 V to 3.3 V translation)

260 Mbit/s ( 1.1 V to 2.5 V translation)

210 Mbit/s ( 1.1 V to 1.8 V translation)

150 Mbit/s ( 1.1 V to 1.5 V translation)

100 Mbit/s ( 1.1 V to 1.2 V translation)

CC(A)

CC(B)

can be supplied at any voltage between 0.8 V and 3.6 V making the device

: 0.8 V to 3.6 V

CC(B)

. A HIGH on DIR allows transmission from An to Bn and a LOW on

CC(A)

and V

and pins Bn are

CC(A)

Product data sheet

CC(B)

OFF

or V

). Both V

. The I

CC(B)

are at

OFF

CC(A)

Related parts for 74AVC8T245BQ

74AVC8T245BQ Summary of contents

Page 1

Rev. 02 — 28 April 2009 1. General description The 74AVC8T245 is an 8-bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports (An ...

... I I OFF I Multiple package options I Speciﬁed from +85 C and +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AVC8T245PW +125 C 74AVC8T245BQ +125 C 4. Functional diagram V V CC(A) CC( DIR 3 A1 Fig 1. Logic symbol ...

Page 3

NXP Semiconductors Fig 2. Logic diagram (one channel) 5. Pinning information 5.1 Pinning 74AVC8T245 V 1 CC(A) 2 DIR GND 11 GND 12 Fig ...

Page 4

NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin V 1 CC(A) DIR [1] GND 11 [1] GND 12 [1] GND 21, ...

Page 5

NXP Semiconductors Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter I ground current GND T storage temperature stg P total power dissipation ...

Page 6

NXP Semiconductors Table 6. Typical static characteristics recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I power-off leakage current OFF C input capacitance I C input/output capacitance I/O [ ...

Page 7

NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level output voltage I = 100 CC(A) I ...

Page 8

NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I supply current A port CC(A) V CC(B) V CC(A) V CC(B) V CC(A) V ...

Page 9

NXP Semiconductors 10. Dynamic characteristics Table 9. Typical dynamic characteristics at V Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t propagation delay disable ...

Page 10

NXP Semiconductors Table 11. Typical power dissipation capacitance at V Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions C power dissipation A port: (direction capacitance Bn); output enabled A port: (direction An to ...

Page 11

NXP Semiconductors Table 12. Dynamic characteristics for temperature range +85 C Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 1.3 V CC(A) t propagation ...

Page 12

NXP Semiconductors Table 13. Dynamic characteristics for temperature range +125 C Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 1.3 V CC(A) t propagation ...

Page 13

NXP Semiconductors 11. Waveforms Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 5. The data input (An, Bn) to output (Bn, An) propagation delay times OE ...

Page 14

NXP Semiconductors Test data is given in Table R = Load resistance Load capacitance including jig and probe capacitance Termination resistance External voltage for measuring switching times. EXT Fig 7. Load ...

Page 15

NXP Semiconductors 12. Typical propagation delay characteristics (ns Propagation delay (An to Bn 0.8 V. CC(B) ( 1.2 V. CC(B) ( ...

Page 16

NXP Semiconductors 7 t PLH (ns LOW to HIGH propagation delay ( 1.2 V CC( PLH (ns LOW to HIGH propagation delay ...

Page 17

NXP Semiconductors 7 t PLH (ns LOW to HIGH propagation delay ( 1.8 V CC( PLH (ns LOW to HIGH propagation delay ...

Page 18

NXP Semiconductors 7 t PLH (ns LOW to HIGH propagation delay ( 3.3 V CC(A) ( 1.2 V. CC(B) ( 1.5 V. CC(B) ( ...

Page 19

NXP Semiconductors 13. Package outline TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. ...

Page 20

NXP Semiconductors DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm terminal 1 index area terminal 1 index area ...

Page 21

NXP Semiconductors 14. Abbreviations Table 16. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 17. Revision history Document ...

Page 22

NXP Semiconductors 16. Legal information 16.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualiﬁcation Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 23

NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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