AT25DF641A-MH-T ATMEL [ATMEL Corporation], AT25DF641A-MH-T Datasheet
AT25DF641A-MH-T
Related parts for AT25DF641A-MH-T
AT25DF641A-MH-T Summary of contents
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... Complies with Full Industrial Temperature Range • Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options – 8-lead SOIC (208-mil wide) – 8-contact Ultra Thin DFN (5mm x 6mm x 0.6mm) 64-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory Atmel AT25DF641A Preliminary 8693A–DFLASH–8/10 ...
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... To take code and data protection to the next level, the AT25DF641A incorporates a sector lock- down mechanism that allows any combination of individual 64-Kbyte sectors to be locked down and become permanently read-only. This addresses the need of certain secure applications that ...
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... The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However recommended that the WP pin also be externally connected to V whenever possible. CC 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary] for more details on protection Asserted State Type Low Input ...
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... GROUND: The ground reference for the power supply. GND should be connected to the GND system ground. Figure 2-1. 8-SOIC (Top View GND 4 Atmel AT25DF641A [Preliminary] 4 pin is used to supply the source voltage to the device. CC voltages may produce spurious results and should not be Figure 2-2. 8 VCC 7 HOLD 6 SCK 5 ...
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... The Memory Architecture Diagram illustrates the breakdown of each erase level as well as the breakdown of each physical sector. 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary] CONTROL AND PROTECTION LOGIC Y-DECODER X-DECODER I/O BUFFERS AND LATCHES SRAM DATA BUFFER Y-GATING FLASH MEMORY ARRAY ® AT25DF641A can be erased 5 ...
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... Block Erase and Suspend Functions (D8h Command) 64KB 64KB (Sector 127) 64KB 64KB (Sector 126) 64KB 64KB (Sector 0) Atmel AT25DF641A [Preliminary] 6 Block Erase Detail 32KB 4KB Block Erase Block Erase Block Address (52h Command) (20h Command) Range 4KB – 000h 4KB – ...
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... The Atmel ler, commonly referred to as the SPI Master. The SPI Master communicates with the AT25DF641A via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO). The AT25DF641A features a dual-input program mode in which the SO pin becomes an input. ...
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... Status Register Commands Read Status Register Write Status Register Byte 1 Write Status Register Byte 2 Miscellaneous Commands Reset Read Manufacturer and Device ID Deep Power-Down Resume from Deep Power-Down Atmel AT25DF641A [Preliminary] 8 Clock Opcode Frequency 1Bh 0001 1011 Up to 100MHz 0Bh 0000 1011 ...
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... A MSB MSB HIGH-IMPEDANCE SO 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary] . The 1Bh opcode allows the highest read performance possible and can be used at any should be reserved to systems employing the Atmel CLK ADDRESS BITS A23-A0 ...
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... When the last byte (7FFFFFh) of the memory array has been read, the device will continue reading back at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array. Atmel AT25DF641A [Preliminary ...
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... A23-A0 and the number of data bytes sent to the device. If less than 256-bytes of data were sent to the device, then the remaining bytes within the page will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is internally self-timed and should take place in a time of t 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary ...
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... HIGH-IMPEDANCE SO Figure 8-2. Page Program SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT25DF641A [Preliminary] 12 “Sector Lockdown” on page or t time to determine if the data bytes have finished programming OPCODE ADDRESS BITS A23- ...
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... CS pin being deasserted on uneven byte boundaries, or because the memory location to be programmed is protected or locked down. 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary] “Write Enable” on page only programming a single byte. ...
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... Any additional data clocked into the device will be ignored. When the CS pin is deas- serted, the device will erase the appropriate block. The erasing of the block is internally self- timed and should take place in a time of t Atmel AT25DF641A [Preliminary time to determine if the data bytes have finished programming. ...
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... When the CS pin is deas- serted, the device will erase the entire memory array. The erasing of the device is internally self- timed and should take place in a time of t 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary] time to determine if the device has finished erasing. At BLKE Block Erase ...
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... To perform a Program/Erase Suspend, the CS pin must first be asserted and the opcode of B0h must be clocked into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the program or Atmel AT25DF641A [Preliminary] 16 time to determine if the device has finished erasing. At ...
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... The state of the WEL bit in the Status Register, as well as the SPRL (Sector Protection Registers Locked) and SLE (Sector Lockdown Enabled) bits, will not be affected. 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary] “Reset” on page 40) is performed while a sector is erase suspended, . The Program Sus- ...
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... Read Status Register Write Status Register (All Opcodes) Miscellaneous Commands Reset Read Manufacturer and Device ID Deep Power-Down Resume from Deep Power-Down Atmel AT25DF641A [Preliminary] 18 Operations Allowed and Not Allowed During a Program or Erase Suspend Operation During Operation During Program Suspend Erase Suspend ...
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... Program/Erase Suspend command must check the status of RES the RDY/BSY bit or the appropriate bit in the Status Register to determine if the previ- ously suspended program or erase operation has resumed. 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary] Program/Erase Suspend ...
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... Status Register will be set to a logical “1”. The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-1. Atmel AT25DF641A [Preliminary] 20 Program/Erase Resume CS 0 ...
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... Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the Sector Protection Register corresponding to the physical sector addressed by 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary] Write Disable CS 0 ...
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... CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation, the state of the Sector Protection Register will be unchanged, and the WEL bit in the Status Register will be reset to a logical “0”. Atmel AT25DF641A [Preliminary] 22 Protect Sector ...
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... Global Protect operation is attempted while a sector is erase or program suspended, the protec- tion operation will abort, the protection states of all sectors in the Flash memory array will not change, and WEL bit in the Status Register will be reset back to a logical “0”. 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary] Unprotect Sector CS 0 ...
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... Status Register will perform a Global Protect and keep the SPRL bit in the logical “0” state. The SPRL bit can, of course, be changed to a logical “1” by writing an FFh if software-lock- ing or hardware-locking is desired along with the Global Protect. Atmel AT25DF641A [Preliminary] 24 Valid SPRL and Global Protect/Unprotect Conditions ...
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... In addition to reading the individual Sector Protection Registers, the Software Protection Status (SWP) bits in the Status Register can be read to determine if all, some, or none of the sectors are software protected (refer to 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary] “Read Status Register” on page 33 , the first byte of data output will not be valid. Therefore, if operat- CLK ...
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... When changing the SPRL bit to a logical “1” from a logical “0” also possible to perform a Global Protect or Global Unprotect at the same time by writing the appropriate values into bits five, four, three, and two of the first byte of the Status Register. Tables 9-4 Atmel AT25DF641A [Preliminary] 26 Read Sector Protection Register 0 1 ...
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... Table 9-4. (Don't Care) Note: Table 9- 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary] Sector Protection Register States Sector Protection Register “n” represents a sector number Hardware and Software Locking SPRL Locking SPRL Change Allowed 0 Can be modified from Hardware 1 Locked ...
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... As a safeguard against accidental or erroneous locking down of sectors, the Sector Lockdown command can be enabled and disabled as needed by using the SLE bit in the Status Register. In addition, the current sector lockdown state can be frozen so that no further modifications to Atmel AT25DF641A [Preliminary] 28 Sector Lockdown Register Values Sector Lockdown Status Sector is not locked down and can be programmed and erased ...
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... When the device aborts the Freeze Sector Lockdown State operation, the WEL bit in the Status Register will be reset to a logical “0”; however, the state of the SLE bit will be unchanged. 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary ...
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... The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 10-3. Read Sector Lockdown Register SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT25DF641A [Preliminary OPCODE ADDRESS BITS A23- ...
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... A23-A0 and the number of data bytes sent to the device. If less than 64-bytes of data were sent to the device, then the remaining bytes within the OTP Security Register will not 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary] OTP Security Register Security Register Byte Number 1 ...
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... Therefore, the contents of the buffer will be altered from its previous state when this command is issued. Figure 10-4. Program OTP Security Register SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT25DF641A [Preliminary ADDRESS BITS A23-A0 DATA IN BYTE ...
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... Status Register as long as the CS pin remains asserted and the clock pin is being pulsed. The data in the Status Register is constantly being updated, so each repeating sequence will output new data. The RDY/BSY status is available for both bytes of the Status Register and is updated for each byte. 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary ...
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... RDY/BSY Ready/Busy Status Notes: 1. Only bit 7 of Status Register Byte 1 will be modified when using the Write Status Register Byte 1 command 2. R/W = Readable and writeable R = Readable only Atmel AT25DF641A [Preliminary the first two bytes of data output from the Status Register will CLK (2) Type ...
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... SPRL bit back to a logical “0” using the Write Status Register Byte 1 command, the WP pin will have to first be deasserted. The SPRL bit is the only bit of Status Register Byte 1 that can be user modified via the Write Sta- tus Register Byte 1 command. 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary] (2) Type Description R 0 Reserved for future use ...
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... In order for the WEL bit to be reset when an operation aborts prematurely, the entire opcode for a Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, or Write Status Register com- mand must have been clocked into the device. Atmel AT25DF641A [Preliminary] 36 8693A–DFLASH–8/10 ...
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... To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data must be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical “1” logical “0”. 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary] 37 ...
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... SPRL bit to a logical “0” while the WP pin is asserted, then the Write Status Register Byte 1 command will be ignored, and the WEL bit in the Status Register will be reset back to the logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted. Table 11-3. Bit 7 SPRL Atmel AT25DF641A [Preliminary ...
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... RSTE and SLE bits will not change, and the WEL bit in the Status Register will be reset back to the logical “0” state. Table 11-4. Bit 7 X 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary ...
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... The complete opcode and confirmation byte must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no Reset operation will be performed. Atmel AT25DF641A [Preliminary ...
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... String Length and any subsequent data is optional. Deasserting the CS pin will terminate the Manufacturer and Device ID read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary ...
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... Device ID (Part Table 12-3. EDI Data Byte Number Bit 7 Bit 6 Bit 5 RFU Figure 12-2. Read Manufacturer and Device ID CS SCK SI SO Atmel AT25DF641A [Preliminary] 42 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 JEDEC Assigned Code Density Code Product Variant ...
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... The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-Down mode. Figure 12-3. Deep Power-Down 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary ...
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... While in the Hold mode, the SO pin will high-impedance state. In addition, both the SI pin and the SCK pin will be ignored. The WP pin, however, can still be asserted or deasserted while in the Hold mode. Atmel AT25DF641A [Preliminary] 44 and return to the standby mode. After the device ...
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... SCK, the host controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host controller should clock its data out on the rising edge of SCK in order to give the AT25DF641A a full clock cycle to latch the incoming data in on the next rising edge of SCK. ...
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... Temperature under Bias .................... -55⋅C to +125⋅C Storage Temperature........................ -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ....................... -0.6V to +4.1V All Output Voltages with Respect to Ground ............... -0. 14.2 DC and AC Operating Range Operating Temperature (Case) V Power Supply CC Atmel AT25DF641A [Preliminary ...
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... Maximum Clock Frequency for 03h Opcode (Read Array – Low Frequency) RDLF f Maximum Clock Frequency for 3Bh Opcode (Dual-Output Read) RDDO 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary] Condition Min CS, WP, HOLD = all inputs at CMOS levels CS, WP, HOLD = V ...
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... Chip Select High to Standby Mode RDPD t Reset Time RST Notes: 1. Not 100% tested (value guaranteed by design and characterization) 2. 15pF load at frequencies above 70MHz, 30pF otherwise 3. Only applicable as a constraint for the Write Status Register Byte 1 command when SPRL = 1 Atmel AT25DF641A [Preliminary] 48 Min Max Units 4.3 ns 4.3 ns ...
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... CC t Power-up Device Delay Before Program or Erase Allowed PUW V Power-on Reset Voltage POR 14.8 Input Test Waveforms and Measurement Levels DRIVING LEVELS t R 14.9 Output Test Load 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary] 4-Kbytes 32-Kbytes 64-Kbytes Program Erase Program Erase 0. 0. < (10% to 90%) ...
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... Figure 15-2. Serial Output Timing CS SCK Figure 15-3. WP Timing for Write Status Register Byte 1 Command When SPRL = WPS WP SCK SI 0 MSB OF WRITE STATUS REGISTER BYTE 1 OPCODE HIGH-IMPEDANCE SO Atmel AT25DF641A [Preliminary CSLH t t CLKH CLKL t DH LSB t CLKH WPH 0 ...
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... Figure 15-4. HOLD Timing – Serial Input CS SCK HOLD SI HIGH-IMPEDANCE SO Figure 15-5. HOLD Timing – Serial Output CS SCK t HHH HOLD SI SO 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary HHH HLS t HLH t HLS t HLH t t HLQZ t HHS t HHS HHQX 51 ...
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... Package AT25DF641A-SH-B 8S2 AT25DF641A-SH-T AT25DF641A-MH-Y 8MA1 AT25DF641A-MH-T Note: The shipping carrier option code is not marked on the devices 8S2 8-lead, 0.208” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8MA1 8-pad 0.6mm Body, Thermally enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) ...
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... Mismatch of the upper and lower dies and resin burrs are not included. 3. Determines the true geometric position. 4. Values b, C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021mm. Package Drawing Contact: packagedrawings@atmel.com 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary TITLE 8S2, 8-lead, 0.208” ...
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... Top View Pin #1 Notch (0.20 R) (Option Bottom View L Notes: 1. This package conforms to JEDEC reference MO-229, Saw Singulation. 2. The terminal # Laser-marked Feature. Package Drawing Contact: packagedrawings@atmel.com Atmel AT25DF641A [Preliminary Option A 1 Pin #1 Chamfer (C 0.35) 2 SYMBOL ...
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... Workaround: None. Devices are limited to the clock frequencies specified above. Resolution: The clock frequency issues are being fixed with a new revision of the device. Please contact Atmel 8693A–DFLASH–8/10 Atmel AT25DF641A [Preliminary] Opcodes Affected Datasheet Specification 1Bh, 3Ch, 35h, 77h, 05h ...
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... Revision History Doc. Rev. 8693A Atmel AT25DF641A [Preliminary] 56 Date Comments 08/2010 Initial document release 8693A–DFLASH–8/10 ...
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Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1) (408) 441-0311 Fax: (+1) (408) 487-2600 www.atmel.com Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel ...