CY62167DV30_06 CYPRESS [Cypress Semiconductor], CY62167DV30_06 Datasheet

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CY62167DV30_06

Manufacturer Part Number
CY62167DV30_06
Description
16-Mbit (1M x 16) Static RAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Cypress Semiconductor Corporation
Document #: 38-05328 Rev. *G
Features
Functional Description
The CY62167DV30 is a high-performance CMOS static RAM
organized as 1M words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
• TSOP I Configurable as 1M x 16 or as 2M x 8 SRAM
• Very high speed: 45 ns
• Wide voltage range: 2.2V – 3.6V
• Ultra-low active power
• Ultra-low standby power
• Easy memory expansion with CE
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free and non Pb-free 48-ball VFBGA
— Typical active current: 2 mA @ f = 1 MHz
— Typical active current: 18.5 mA @ f = f
and 48-pin TSOP I package
speed)
A
A
A
A
A
A
A
A
A
A
A
10
9
8
7
6
5
4
3
2
1
0
[1]
Power-Down
Circuit
COLUMN DECODER
1
DATA IN DRIVERS
, CE
1M × 16 / 2M x 8
RAM Array
2
and OE features
Max
198 Champion Court
(45 ns
®
) in
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE
HIGH). The input/output pins (I/O
in a high-impedance state when: deselected (CE
LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a Write operation (CE
LOW).
Writing to the device is accomplished by taking Chip Enables
(CE
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O
through I/O
address pins (A
LOW, then data from I/O pins (I/O
the location specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enables (CE
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O
High Enable (BHE) is LOW, then data from memory will appear
on I/O
sheet for a complete description of Read and Write modes.
BHE
BLE
16-Mbit (1M x 16) Static RAM
1
LOW and CE
8
to I/O
San Jose
7
), is written into the location specified on the
1
15
LOW and CE
1
. See the truth table at the back of this data
0
HIGH or CE
through A
2
HIGH) and Write Enable (WE) input LOW.
,
I/O
I/O
CA 95134-1709
OE
BLE
BYTE
BHE
WE
CY62167DV30 MoBL
0
8
–I/O
–I/O
19
2
2
CE
CE
HIGH) and Output Enable (OE)
). If Byte High Enable (BHE) is
LOW or both BHE and BLE are
7
15
2
1
8
Revised July 27, 2006
1
0
through I/O
LOW, CE
through I/O
CE
CE
2
1
2
0
15
through A
0
HIGH and WE
15
) is written into
408-943-2600
1
to I/O
HIGH or CE
) are placed
7
. If Byte
19
).
®
2
0
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CY62167DV30_06 Summary of contents

Page 1

... LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O High Enable (BHE) is LOW, then data from memory will appear on I/O to I/O . See the truth table at the back of this data ...

Page 2

Product Portfolio V Range (V) CC [2] Product Min. Typ. CY62167DV30LL 2.2 3.0 [ Pin Configuration A15 1 A14 2 A13 3 A12 4 A11 5 A10 A19 ...

Page 3

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ..................................–65°C to +150°C Ambient Temperature with Power Applied .............................................–55°C to +125°C Supply Voltage to Ground Potential ...... –0. Voltage ...

Page 4

Capacitance Parameter Description C Input Capacitance IN C Output Capacitance OUT [10] Thermal Resistance Parameter Description Θ Thermal Resistance JA (Junction to Ambient) Θ Thermal Resistance JC (Junction to Case) AC Test Loads and Waveforms ...

Page 5

... HZCE HZBE HZWE 18. The internal Write time of the memory is defined by the overlap of WE write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the Write. ...

Page 6

Switching Waveforms Read Cycle 1 (Address Transition Controlled) ADDRESS PREVIOUS DATA VALID DATA OUT [20, 21] Read Cycle 2 (OE Controlled) ADDRESS ACE BHE/BLE t LZBE OE t LZOE HIGH IMPEDANCE DATA OUT t LZCE ...

Page 7

Switching Waveforms (continued) [18, 22, 23, 24] Write Cycle 1 (WE Controlled) ADDRESS BHE/BLE OE DATA I/O See Note 23 t HZOE Notes: 22. Data I/O is high-impedance ...

Page 8

Switching Waveforms (continued) Write Cycle 2 ( Controlled ADDRESS BHE/BLE OE DATA I/O See Note 23 t HZOE Write Cycle 3 (WE Controlled, OE LOW) ADDRESS BHE/BLE ...

Page 9

Switching Waveforms (continued) Write Cycle 4 (BHE/BLE Controlled, OE LOW) ADDRESS BHE/BLE DATA I/O See Note 23 Truth Table BHE ...

Page 10

Ordering Information Speed Ordering Code (ns) 45 CY62167DV30LL-45ZXI 55 CY62167DV30LL-55BVI CY62167DV30LL-55BVXI CY62167DV30LL-55ZI CY62167DV30LL-55ZXI 70 CY62167DV30LL-70BVI Please contact your local Cypress sales representative for availability of these parts Package Diagrams TOP VIEW A1 CORNER ...

Page 11

Package Diagrams (continued) DIMENSIONS IN INCHES[MM] MIN. MAX. JEDEC # MO-142 1 0.004[0.10] 0.008[0.21] 0°-5° MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document ...

Page 12

Document History Page Document Title: CY62167DV30 MoBL Document Number: 38-05328 Orig. of REV. ECN NO. Issue Date Change ** 118408 09/30/02 *A 123692 02/11/03 *B 126555 04/25/03 *C 127841 09/10/03 *D 205701 *E 238050 See ECN KKV/AJU Replaced 48-ball VFBGA ...

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