NAND01G-A STMICROELECTRONICS [STMicroelectronics], NAND01G-A Datasheet

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NAND01G-A

Manufacturer Part Number
NAND01G-A
Description
128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
FEATURES SUMMARY
February 2005
HIGH DENSITY NAND FLASH MEMORIES
NAND INTERFACE
SUPPLY VOLTAGE
PAGE SIZE
BLOCK SIZE
PAGE READ / PROGRAM
COPY BACK PROGRAM MODE
FAST BLOCK ERASE
STATUS REGISTER
ELECTRONIC SIGNATURE
CHIP ENABLE ‘DON’T CARE’ OPTION
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
Up to 1 Gbit memory array
Up to 32 Mbit spare area
Cost effective solutions for mass storage
applications
x8 or x16 bus width
Multiplexed Address/ Data
Pinout compatibility for all densities
1.8V device: V
3.0V device: V
x8 device: (512 + 16 spare) Bytes
x16 device: (256 + 8 spare) Words
x8 device: (16K + 512 spare) Bytes
x16 device: (8K + 256 spare) Words
Random access: 12µs (max)
Sequential access: 50ns (min)
Page program time: 200µs (typ)
Fast page copy without external buffering
Block erase time: 2ms (Typ)
Simple interface with microcontroller
Program/Erase locked during Power
transitions
528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
DD
DD
= 1.7 to 1.95V
= 2.7 to 3.6V
128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16)
NAND512-A, NAND01G-A
NAND128-A, NAND256-A
Figure 1. Packages
DATA INTEGRITY
RoHS COMPLIANCE
DEVELOPMENT TOOLS
100,000 Program/Erase cycles
10 years Data Retention
Lead-Free Components are Compliant
with the RoHS Directive
Error Correction Code software and
hardware models
Bad Blocks Management and Wear
Leveling algorithms
File System OS Native reference software
Hardware simulation models
TFBGA55 8 x 10 x 1.2mm
TFBGA63 9 x 11 x 1.2mm
VFBGA55 8 x 10 x 1mm
VFBGA63 9 x 11 x 1mm
USOP48 12 x 17 x 0.65mm
TSOP48 12 x 20mm
FBGA
1/57

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NAND01G-A Summary of contents

Page 1

... Simple interface with microcontroller SERIAL NUMBER OPTION HARDWARE DATA PROTECTION – Program/Erase locked during Power transitions February 2005 NAND128-A, NAND256-A NAND512-A, NAND01G-A 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) Figure 1. Packages DATA INTEGRITY – – RoHS COMPLIANCE – DEVELOPMENT TOOLS – ...

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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 1. Product List Reference NAND128-A NAND256-A NAND512-A NAND01G-A 2/57 Part Number NAND128R3A NAND128W3A NAND128R4A NAND128W4A NAND256R3A NAND256W3A NAND256R4A NAND256W4A NAND512R3A NAND512W3A NAND512R4A NAND512W4A NAND01GR3A NAND01GW3A NAND01GR4A NAND01GW4A ...

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... Chip Enable ( Read Enable (R Write Enable (W Write Protect (WP Ready/Busy (RB Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SS BUS OPERATIONS Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 6. Address Insertion, x8 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 NAND128-A, NAND256-A, NAND512-A, NAND01G-A 3/57 ...

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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 7. Address Insertion, x16 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 8. Address Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 COMMAND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DEVICE OPERATIONS Pointer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 11.Pointer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 12.Pointer Operations for Programming Read Memory Array Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Page Read Sequential Row Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 13.Read (A,B,C) Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 14 ...

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... Figure 41.VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . . . 51 Table 26. VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data . . 51 Figure 42.TFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline Table 27. TFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data . . 52 NAND128-A, NAND256-A, NAND512-A, NAND01G-A 5/57 ...

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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 28. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 APPENDIX A.HARDWARE INTERFACE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 43.Connection to Microcontroller, Without Glue Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 44.Connection to Microcontroller, With Glue Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 45.Building Storage Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 REVISION HISTORY Table 29. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6/57 ...

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... When a Page Program operation fails, the data can be pro- grammed in another page without having to re- send the data to be programmed. NAND128-A, NAND256-A, NAND512-A, NAND01G-A The devices are available in the following packag- es: TSOP48 12 x 20mm for all products USOP48 0.65mm for 128Mb, 256Mb ...

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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 2. Product Description Reference Part Number Density Width NAND128R3A NAND128W3A NAND128-A 128Mbit NAND128R4A NAND128W4A NAND256R3A NAND256W3A NAND256-A 256Mbit NAND256R4A NAND256W4A NAND512R3A NAND512W3A (1) 512Mbit NAND512-A NAND512R4A NAND512W4A NAND512R3A NAND512W3A NAND512-A 512Mbit NAND512R4A NAND512W4A NAND01GR3A NAND01GW3A NAND01G-A 1Gbit NAND01GR4A NAND01GW4A Note: 1 ...

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... Figure 3. Logic Block Diagram Address Register/Counter Command Interface E Logic WP R Command Register NAND128-A, NAND256-A, NAND512-A, NAND01G-A NAND Flash Memory Array P/E/R Controller, High Voltage Generator Page Buffer Y Decoder I/O Buffers & Latches RB I/O0-I/O7, x8/x16 I/O8-I/O15, x16 AI07561c 9/57 ...

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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 4. TSOP48 and USOP48 Connections, x8 devices NAND Flash (x8 10/57 Figure 5. TSOP48 and USOP48 Connections, x16 devices I/O7 NC I/O6 NC I/O5 I/ ...

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... Figure 6. FBGA55 Connections, x8 devices (Top view through package NAND128-A, NAND256-A, NAND512-A, NAND01G I/ I/ I/O2 I/O3 I/ ...

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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 7. FBGA55 Connections, x16 devices (Top view through package 12/ I/O5 I/O8 I/O1 I/O10 I/O12 I/ I/O2 I/O11 I/ ...

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... Figure 8. FBGA63 Connections, x8 devices (Top view through package NAND128-A, NAND256-A, NAND512-A, NAND01G I/ I/ I/O2 I/O3 I/ ...

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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 9. FBGA63 Connections, x16 devices (Top view through package I/ 14/ I/O5 I/O1 I/O10 I/O12 V DD I/O9 I/O3 I/O2 I/O11 I/ ...

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... Block Page 512 Bytes Page Buffer, 512 Bytes 512 Bytes NAND128-A, NAND256-A, NAND512-A, NAND01G-A The Bad Block Information is written prior to ship- ping (refer to more details). Table 4. blocks in each device. The values shown include both the Bad Blocks that are present when the de- vice is shipped and the Bad Blocks that could de- velop later on ...

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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram, 3., Signal Names, for a brief overview of the sig- nals connected to this device. Inputs/Outputs (I/O0-I/O7). Input/Outputs are used to input the selected address, output the data during a Read operation or input a command or data during a Write operation. The inputs are latched on the rising edge of Write Enable ...

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... Note: 1. Only for x16 devices must be V when issuing a program or erase command. IH NAND128-A, NAND256-A, NAND512-A, NAND01G-A Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the Write Enable signal ...

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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 6. Address Insertion, x8 Devices Bus Cycle I/O7 I/ A16 A15 2 rd A24 A23 3 th( Note set Low or High by the 00h or 01h Command, see 2. Any additional address input cycles will be ignored. 3. The 4th cycle is only required for 512Mb and 1Gb devices. ...

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... Reset Note: 1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown. 2. Any undefined command sequence will be ignored by the device. NAND128-A, NAND256-A, NAND512-A, NAND01G-A mand Register. sequences for program and erase operations are imposed to maximize data security ...

Page 20

... NAND128-A, NAND256-A, NAND512-A, NAND01G-A DEVICE OPERATIONS Pointer Operations As the NAND Flash memories contain two differ- ent areas for x16 devices and three different areas for x8 devices (see Figure 11.) the read command codes (00h, 01h, 50h) are used to act as pointers to the different areas of the memory array (they se- lect the most significant column address) ...

Page 21

... Areas B, C can be programmed depending on how much data is input. The 01h command must be re-issued before each program. Address 80h I/O 50h Inputs Only Areas C can be programmed. Subsequent 50h commands can be omitted. NAND128-A, NAND256-A, NAND512-A, NAND01G-A AREA A Data Input 10h 80h 00h AREA B ...

Page 22

... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Read Memory Array Each operation to read the memory area starts with a pointer operation as shown in the Operations section. Once the area (main or spare) has been selected using the Read A, Read B or Read C commands four bus cycles (for 512Mb ...

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... Area A (2nd half Page) (1st half Page) A9-A26 (1) A0-A7 Read B Command, X8 Devices Area A (2nd half Page) (1st half Page) A9-A26 (1) A0-A7 Note: 1. Highest address depends on device density. NAND128-A, NAND256-A, NAND512-A, NAND01G-A tBLBH1 (read) Address Input Busy Area B Area C (Spare) A9-A26 (1) A0-A7 Area B Area C (Spare) ...

Page 24

... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 15. Sequential Row Read Operations tBLBH1 (Read Busy time) RB 00h/ I/O Address Inputs 01h/ 50h Command Code Figure 16. Sequential Row Read Block Diagrams Read A Command, x8 Devices Area B Area A (2nd half Page) (1st half Page) Block Read B Command, x8 Devices ...

Page 25

... Page Program Setup Code Note: Before starting a Page Program operation a Pointer operation can be performed. Refer to NAND128-A, NAND256-A, NAND512-A, NAND01G-A 3. the data is then input (up to 528 Bytes/ 264 Words) and loaded into the Page Buffer 4. one bus cycle is required to issue the confirm command to start the P/E/R Controller ...

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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Copy Back Program The Copy Back Program operation is used to copy the data stored in one page and reprogram it in an- other page. The Copy Back Program operation does not re- quire external memory and so the operation is faster and more efficient because the reading and loading cycles are not required ...

Page 27

... NAND128-A, NAND256-A, NAND512-A, NAND01G-A are required to input the block address. The first cycle (A0 to A7) is not required as only addresses A14 to A26 (highest address depends on device density) are valid A13 are ignored ...

Page 28

... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Read Status Register The device contains a Status Register which pro- vides information on the current or previous Pro- gram or Erase operation. The various bits in the Status Register convey information and errors on the operation. The Status Register is read by issuing the Read Status Register command ...

Page 29

... Bus Read operations – the first will read the Manufacturer Code and the second, the Device Code. Further Bus Read operations will be ignored. Refer to Table 12., Electronic mation on the addresses. NAND128-A, NAND256-A, NAND512-A, NAND01G-A Logic Level '1' '0' '1' '0' Don’t Care ‘ ...

Page 30

... NAND128-A, NAND256-A, NAND512-A, NAND01G-A SOFTWARE ALGORITHMS This section gives information on the software al- gorithms that ST recommends to implement to manage the Bad Blocks and extend the lifetime of the NAND device. NAND Flash memories are programmed and erased by Fowler-Nordheim tunneling using a high voltage. Exposing the device to a high voltage for extended periods can cause the oxide layer to be damaged ...

Page 31

... The Second Level Wear-leveling is triggered when the difference between the maximum and the min- imum number of write cycles per block reaches a specific threshold. NAND128-A, NAND256-A, NAND512-A, NAND01G-A Old Area New Area (After GC) Free Page (Erased) ...

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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Hardware Simulation Models Behavioral simulation models. Denali Software Corporation models are platform independent functional models designed to assist customers in performing entire system simulations (typical VHDL/Verilog). These models describe the logic behavior and timings of NAND Flash devices, and so allow software to be developed before hard- ware ...

Page 33

... V Supply Voltage DD Note: 1. Minimum Voltage may undershoot to –2V for less than 20ns during transitions on input and I/O pins. Maximum voltage may over- shoot for less than 20ns during transitions on I/O pins. DD NAND128-A, NAND256-A, NAND512-A, NAND01G-A Ta- NAND Flash Min 100,000 10 Ta- not implied. Exposure to Absolute Maximum Rat- ...

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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC characteristics Tables that follow, are de- rived from tests performed under the Measure- Table 16. Operating and AC Measurement Conditions ...

Page 35

... Input Low Voltage IL V Output High Voltage Level OH V Output Low Voltage Level OL I (RB) Output Low Current (RB Supply Voltage (Erase and DD V LKO Program lockout) NAND128-A, NAND256-A, NAND512-A, NAND01G-A Test Conditions t minimum Sequential RLRL Read E IL, OUT Program - Erase - E=V -0.2, ...

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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 19. DC Characteristics, 3V Devices Symbol Parameter I DD1 Operating I Current DD2 I DD3 Stand-by Current (TTL), 128Mb, 256Mb, 512Mb devices I DD4 Stand-by Current (TTL) 512Mb and 1Gb Dual Die devices Stand-By Current (CMOS) 128Mb, 256Mb, 512Mb devices I DD5 Stand-By Current (CMOS) ...

Page 37

... Write Enable Low to Write Enable Low WLWL WC Note less than 10ns, t ELWL WLWH NAND128-A, NAND256-A, NAND512-A, NAND01G-A Parameter AL Setup time CL Setup time Data Setup time E Setup time AL Hold time CL hold time Data Hold time E Hold time W High Hold ...

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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 21. AC Characteristics for Operations Alt. Symbol Symbol t ALLRL1 Address Latch Low Read Enable Low t ALLRL2 t t Ready/Busy High to Read Enable Low BHRL RR t BLBH1 Ready/Busy Low Ready/Busy High BLBH2 PROG t t BLBH3 BERS t BLBH4 ...

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... Setup time) E tWLWH W tALHWL (AL Setup time) (AL Hold time) AL tDVWH (Data Setup time) I/O Note: Address cycle 4 is only required for 512Mb and 1Gb devices. NAND128-A, NAND256-A, NAND512-A, NAND01G-A tWLWH tDVWH (Data Setup time) Command tCLLWL (CL Setup time) tWLWL tWLWL tWLWH tWLWH tWHWL ...

Page 40

... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 25. Data Input Latch AC Waveforms CL E tALLWL (ALSetup time) AL tWLWH W (Data Setup time) I/O Figure 26. Sequential Data Output after Read AC Waveforms E R tRLQV (R Accesstime) I/O tBHRL RB Note Low Low High. 40/57 tWLWL tWLWH tDVWH tDVWH tWHDX (Data Hold time) ...

Page 41

... Figure 28. Read Electronic Signature AC Waveform I/O 90h Read Electronic Signature Command Note: Refer to Table 12. for the values of the Manufacturer and Device Codes. NAND128-A, NAND256-A, NAND512-A, NAND01G-A tCLLRL tWHCLL tWHEH tWLWH tWHRL tDZRL tDVWH tWHDX (Data Hold time) 70h tALLRL1 tRLQV (Read ES Access time) Man ...

Page 42

... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 29. Page Read A/ Read B Operation AC Waveform CL E tWLWL 00h or Add.N I/O 01h cycle 1 Command Code Note: Address cycle 4 is only required for 512Mb and 1Gb devices. 42/57 tWHBL tALLRL2 tWHBH tRLRH tBLBH1 Data Add.N Add.N Add.N cycle 2 ...

Page 43

... Add. M I/O 50h cycle 1 RB Command Code Note: 1. A0-A7 is the address in the Spare Memory area, where A0-A3 are valid and A4-A7 are ‘don’t care’. NAND128-A, NAND256-A, NAND512-A, NAND01G-A tWHALL Add. M Add. M Add. M cycle 2 cycle 3 cycle 4 Address M Input Busy tWHBH tALLRL2 ...

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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 31. Page Program AC Waveform CL E tWLWL (Write Cycle time Add.N I/O 80h cycle 1 RB Page Program Setup Code Note: Address cycle 4 is only required for 512Mb and 1Gb devices. 44/57 tWLWL tWHBL Add.N Add.N Add.N N cycle 4 cycle 2 cycle 3 ...

Page 45

... Block Erase Setup Command Note: Address cycle 3 is required for 512Mb and 1Gb devices only. Figure 33. Reset AC Waveform I/O FFh RB NAND128-A, NAND256-A, NAND512-A, NAND01G-A tWHBL (Erase Busy time) Add. Add. D0h cycle 2 cycle 3 Confirm Block Erase Block Address Input Code ...

Page 46

... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Ready/Busy Signal Electrical Characteristics Figures 35, 34 and 36 show the electrical charac- teristics for the Ready/Busy signal. The value re- quired for the resistor R can be calculated using P the following equation: V DDmax V OLmax – min = ----------------------------------------------------------- - So, 1.85V R P min 1.8V ...

Page 47

... Table 22. TSOP48 - 48 lead Plastic Thin Small Outline 20mm, Package Mechanical Data Symbol Typ A A1 0.100 A2 1.000 B 0.220 12.000 E 20.000 E1 18.400 e 0.500 L 0.600 L1 0.800 3° NAND128-A, NAND256-A, NAND512-A, NAND01G millimeters Min Max 1.200 0.050 0.150 0.950 1.050 0.170 0.270 0.100 0.210 0.080 11.900 12.100 19.800 20.200 18 ...

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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 38. USOP48 – lead Plastic Ultra Thin Small Outline,12 x 17mm, Package Outline DIE Note: Drawing not to scale. Table 23. USOP48 – lead Plastic Ultra Thin Small Outline 17mm, Package Mechanical Data Symbol Typ 0.52 b 0. ...

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... Table 24. VFBGA55 8 x 10mm - 6x8 ball array, 0.80mm pitch, Package Mechanical Data Symbol Typ 0.45 D 8.00 D1 4.00 D2 5.60 ddd E 10.00 E1 5.60 E2 8.80 e 0.80 FD 2.00 FD1 1.20 FE 2.20 FE1 0.60 SD 0.40 SE 0.40 NAND128-A, NAND256-A, NAND512-A, NAND01G FE1 FD1 millimeters Min Max 1.05 0.25 0.70 0.40 0.50 7.90 8.10 0.10 9.90 10.10 – – E ddd A2 BGA-Z61 inches ...

Page 50

... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 40. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Outline SE FE Note: Drawing is not to scale Table 25. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical Data Symbol Typ 0.80 b 0.45 D 8.00 D1 4.00 D2 5.60 ddd E 10. ...

Page 51

... Table 26. VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data Symbol Typ 0.45 D 9.00 D1 4.00 D2 7.20 ddd E 11.00 E1 5.60 E2 8.80 e 0.80 FD 2.50 FD1 0.90 FE 2.70 FE1 1.10 SD 0.40 SE 0.40 NAND128-A, NAND256-A, NAND512-A, NAND01G FE1 millimeters Min Max 1.05 0.25 0.70 0.40 0.50 8.90 9.10 0.10 10.90 11.10 – – – – – – FE ddd A2 ...

Page 52

... NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 42. TFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline FD1 BALL "A1" Note: Drawing is not to scale Table 27. TFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data Symbol Typ 0. ...

Page 53

... F = Lead Free Package, Tape & Reel Packing Devices are shipped from the factory with the memory content bits, in valid blocks, erased to ’1’. For further information on any aspect of this device, please contact your nearest ST Sales Office. NAND128-A, NAND256-A, NAND512-A, NAND01G-A NAND512R3A 0 ...

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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A APPENDIX A. HARDWARE INTERFACE EXAMPLES Nand Flash devices can be connected to a micro- controller system bus for code and data storage. For microcontrollers that have an embedded NAND controller the NAND Flash can be connect- ed without the addition of glue logic (see Figure 43 ...

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... CL AL NAND Flash NAND Flash W Device RELATED DOCUMENTATION STMicroelectronics has published a set of application notes to support the NAND Flash memories. They are available from the ST Website www.st.com . or from your local ST Distributor. NAND128-A, NAND256-A, NAND512-A, NAND01G-A CLK D flip-flop ...

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... NAND128-A, NAND256-A, NAND512-A, NAND01G-A REVISION HISTORY Table 29. Document Revision History Date Version 06-Jun-2003 1.0 First Issue 07-Aug-2003 2.0 Design Phase 27-Oct-2003 3.0 Engineering Phase Document promoted from Target Specification to Preliminary Data status. V 03-Dec-2003 4.0 Title of for NANDXXXR3A devices corrected. WSOP48 and VFBGA55 packages added, VFBGA63 ( 1mm) removed. ...

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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America NAND128-A, NAND256-A, NAND512-A, NAND01G-A All other names are the property of their respective owners © ...

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