NAND04GA3C2A STMICROELECTRONICS [STMicroelectronics], NAND04GA3C2A Datasheet
NAND04GA3C2A
Related parts for NAND04GA3C2A
NAND04GA3C2A Summary of contents
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... Data Retention ECOPACK Development tools – Bad Blocks Management and Wear Leveling algorithms – File System OS Native reference software – Hardware simulation models Part Number NAND04GA3C2A NAND04GW3C2A Rev 2 NAND04GA3C2A NAND04GW3C2A TSOP48 12 x 20mm ® package available Density 4 Gbits www.st.com 1/51 1 ...
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... Write Enable ( 3.7 Write Protect (WP 3.8 Ready/Busy (RB 3.9 V supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DD 3.10 V ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SS 3.11 VSSQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.12 VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/51 NAND04GA3C2A, NAND04GW3C2A ...
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... NAND04GA3C2A, NAND04GW3C2A 6.3 Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 Cache Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.5 Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.6 Sequential Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.7 Random Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.8 Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.10 Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.10.1 6.10.2 6.10.3 6.10.4 6.10.5 6.11 Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 Embedded ECC accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2 Block replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 ...
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... Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4/51 NAND04GA3C2A, NAND04GW3C2A ...
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... NAND04GA3C2A, NAND04GW3C2A List of tables Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 6. Address insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 7. Address Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 9. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 10. Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 11. Electronic Signature Byte Table 12. ...
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... Block Erase AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 22. Reset AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 23. Program/Erase Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 24. Program/Erase Disable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 25. Ready/Busy AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 26. Ready/Busy Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 27. Resistor Value Versus Waveform Timings For Ready/Busy Signal . . . . . . . . . . . . . . . . . . 47 Figure 28. TSOP48 - 48 lead Plastic Thin Small Outline mm, Package Outline . . . . . . . . . . 48 6/51 NAND04GA3C2A, NAND04GW3C2A ...
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... For more details of this option contact your nearest ST Sales office. The NAND04GA3C2A and NAND04GW3C2A are available in a TSOP48 (12 x 20mm) package. In order to meet environmental requirements, ST offers the devices in ECOPACK packages. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97 ...
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... Summary description Figure 1. Logic Block Diagram Address Register/Counter Command E Interface Logic WP R Command Register Data Register 8/51 NAND04GA3C2A, NAND04GW3C2A NAND Flash Memory Array P/E/R Controller High Voltage Generator Page Buffer Cache Register Y Decoder Buffers RB I/O AI11009b ...
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... NAND04GA3C2A, NAND04GW3C2A Figure 2. Logic diagram Table 3. Signal Names I/ DDQ SSQ DDQ NAND04GA3C2A NAND04GW3C2A SSQ Data Input / Outputs Command latch enable Address latch enable Chip Enable Read Enable Write Enable ...
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... Summary description Figure 3. TSOP48 Connections x8 devices 10/ NAND04GA3C2A NAND04GW3C2A NAND04GA3C2A, NAND04GW3C2A I/O7 I/O6 I/O5 I/ DDQ V SSQ I/O3 I/O2 I/O1 I/ AI12703b ...
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... Figure 4: Memory Array 2.1 Bad blocks The NAND04GA3C2A and NAND04GW3C2A devices may contain Bad Blocks, that is blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional Bad Blocks may develop during the lifetime of the device. The Bad Block Information is written prior to shipping (refer to management for more details) ...
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... Memory array organization Figure 4. Memory Array Organization Block Page 12/51 NAND04GA3C2A, NAND04GW3C2A Block = 128 Pages Page = 2112 Bytes (2,048 + 64) Main Area 8 bits 2048 Bytes 64 Bytes Page Buffer, 2112 Bytes 64 2,048 Bytes 8 bits Bytes AI12704 ...
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... NAND04GA3C2A, NAND04GW3C2A 3 Signal Descriptions See Figure 1: Logic Block signals connected to this device. 3.1 Inputs/outputs (I/O0-I/O7) Input/Outputs are used to input the selected address, output the data during a Read operation or input a command or data during a Write operation. The inputs are latched on the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or the outputs are disabled ...
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... I/O power supply. It must be connected to the system SSQ ground. 3.12 V DDQ V provides power to the I/O buffers. DDQ 14/51 NAND04GA3C2A, NAND04GW3C2A , the device does not accept any IL , during power-up and power-down read, program or erase operation is in progress. When the for details on how to ...
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... NAND04GA3C2A, NAND04GW3C2A 4 Bus operations There are six standard bus operations that control the memory. Each of these is described in this section, see Typically, glitches of less than Chip Enable, Write Enable and Read Enable are ignored by the memory and do not affect bus operations. ...
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... Falling (1) I/O5 I/O4 I/ A11 IL IL A17 A16 A15 A25 A24 A23 NAND04GA3C2A, NAND04GW3C2A W WP I/O0 - I/O7 (1) Rising X Command Rising X Address Rising V Data Input Data Output I/O2 I/ A10 A9 A14 A13 A22 ...
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... NAND04GA3C2A, NAND04GW3C2A 5 Command Set All bus write operations to the device are interpreted by the Command Interface. The Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. Device operations are selected by writing specific commands to the Command Register. The two-step command sequences for program and erase operations are imposed to maximize data security ...
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... Random Data Output command. The Random Data Output command can be issued as many times as required within a page. The Random Data Output command is not accepted during Cache Read operations. 18/51 Table 8: Commands. Once a Read command is (refer to Table 20 for value). Once the transfer is complete the WHBH NAND04GA3C2A, NAND04GW3C2A ...
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... NAND04GA3C2A, NAND04GW3C2A Figure 5. Read Operations I/O Address Input 00h Command Code 1. Highest address depends on device density. tBLBH1 30h Data Output (sequentially) Command Busy Code 6 Device operations Ai11016 19/51 ...
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... The Start Address must be at the beginning of a page (Column Address = 000h, see 7.). This allows the data to be output uninterrupted after the latency time (t Figure 7. 20/51 Busy 05h Data Output Cmd Code Col Add 1,2 Spare Area NAND04GA3C2A, NAND04GW3C2A Address E0h Data Output Inputs Cmd Code 2Add cycles Spare Main Area Area Table ...
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... NAND04GA3C2A, NAND04GW3C2A The Ready/Busy signal can be used to monitor the start of the operation. During the latency period the Ready/Busy signal goes Low, after this the Ready/Busy signal goes High, even if the device is internally downloading page n+1. Once the Cache Read operation has started, the Status Register can be read using the Read Status Register command ...
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... The device remains in Read Status Register mode until another valid command is written to the Command Interface. Figure 8. Page Program Operation RB I/O 80h Page Program Setup Code 22/51 Data Input Address Inputs NAND04GA3C2A, NAND04GW3C2A Table Table Table tBLBH2 (Program Busy time) Busy 10h 70h SR0 Confirm Read Status Register Code 6) ...
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... NAND04GA3C2A, NAND04GW3C2A Figure 9. Random Data Input During Sequential Data Input RB Address I/O 80h Data Intput Inputs Cmd Code 5 Add cycles Row Add 1,2,3 Col Add 1,2 Main Area 6.8 Block Erase Erase operations are done one block at a time. An erase operation sets all of the bits in the addressed block to ‘ ...
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... If the Write Protection bit is set to ‘0’ the device is protected and program or erase operations are not allowed. 24/51 Block Address D0h Inputs Confirm Code after the Reset command is issued. The value WHBH1 for the values. NAND04GA3C2A, NAND04GW3C2A tBLBH3 (Erase Busy time) Busy 70h SR0 Read Status Register ai07593 ...
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... NAND04GA3C2A, NAND04GW3C2A 6.10.2 P/E/R Controller and Cache Ready/Busy Bit (SR6) Status Register bit SR6 has two different functions depending on the current operation. During Cache Read operations SR6 acts as a Cache Ready/Busy bit, which indicates whether the Cache Register is ready to accept new data. When SR6 is set to '0', the Cache Register is busy and when SR6 is set to '1', the Cache Register is ready to accept new data ...
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... P/E/R C active Don’t Care ‘1’ Error – operation failed ‘0’ No Error – operation successful Byte/Word 1 Byte/Word 2 Manufacturer Device code Code 20h DCh 20h DCh NAND04GA3C2A, NAND04GW3C2A Definition Table 10: Electronic Byte 3 Byte 4 (see Table 11) (see Table 84h 25h 84h 12) ...
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... NAND04GA3C2A, NAND04GW3C2A Table 11. Electronic Signature Byte 3 I/O I/O1-I/O0 I/O3-I/O2 I/O5-I/O4 I/O7-I/O6 Table 12. Electronic Signature Byte 4 I/O I/O1-I/O0 I/O2 I/O7, I/O3 I/O5-I/O4 I/O6 Definition Internal Chip number Cell Type Number of simultaneously programmed pages Reserved Definition Page size (Without Spare Area) Spare area size (Byte / 512 Byte) Minimum sequential access time Block size (without Spare Area) ...
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... Embedded ECC accelerator The NAND04GA3C2A and NAND04GW3C2A devices include a powerful embedded Error Correction Code (ECC) accelerator. This feature ensures high memory reliability and fast data throughput while simplifying the design of the memory application. If the embedded ECC accelerator cannot be used strongly recommended to use an external hardware accelerator to maintain the same data throughput ...
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... NAND04GA3C2A, NAND04GW3C2A 9 Software algorithms This section gives information on the software algorithms that ST recommends to implement to manage the Bad Blocks and extend the lifetime of the NAND device. NAND Flash memories are programmed and erased by Fowler-Nordheim tunneling using a high voltage. Exposing the device to a high voltage for extended periods can cause the oxide layer to be damaged ...
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... Invalid Page 30/51 Recommended Procedure Block Replacement Block Replacement or ECC START Block Address = Block 0 Increment Block Address Data Update NO Bad Block table = FFh? YES Last NO block? YES END Old Area New Area (After GC) Free Page (Erased) NAND04GA3C2A, NAND04GW3C2A (1) (1) ECC AI07588C AI07599B ...
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... NAND04GA3C2A, NAND04GW3C2A 9.3 Garbage collection When a data page needs to be modified faster to write to the first available page, and the previous page is marked as invalid. After several updates it is necessary to remove invalid pages to free some memory space. To free this memory space and allow further program operations it is recommended to implement a Garbage Collection algorithm ...
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... These models provide information such as AC characteristics, rise/fall times and package mechanical data, all of which are measured or simulated at voltage and temperature ranges wider than those allowed by target specifications. IBIS models are used to simulate PCB connections and can be used to resolve compatibility issues when upgrading devices. They can be imported into SPICETOOLS. 32/51 NAND04GA3C2A, NAND04GW3C2A ...
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... Table 14 Table 14. Program, Erase Times and Program Erase Endurance Cycles Parameters Page Program Time Block Erase Time Program/Erase Cycles (per block) Data Retention 10 Program and erase times and endurance cycles NAND04GA3C2A, NAND04GW3C2A Min Typ 800 1.5 10,000 10 Unit Max 2000 µs ...
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... IO V Supply Voltage DD 1. Minimum Voltage may undershoot to –2V for less than 20ns during transitions on input and I/O pins. Maximum voltage may overshoot for less than 20ns during transitions on I/O pins. DD 34/51 NAND04GA3C2A, NAND04GW3C2A Table 15: Absolute Maximum Parameter 1.8V, V devices DDQ devices DDQ ...
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... NAND04GA3C2A, NAND04GW3C2A 12 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 16: Operating and AC Measurement operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...
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... Devices DDQ Test Conditions t minimum Sequential RLRL Read E IL, OUT Program - Erase - E=V , WP=0 E=V -0.2, DD WP=0 3. 3.6V OUT - - I = -400µ 2.1mA 0.4V OL NAND04GA3C2A, NAND04GW3C2A Min Typ Max - ± ±10 2 +0.3 DD -0.3 - 0 Unit µ ...
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... NAND04GA3C2A, NAND04GW3C2A Table 19. AC Characteristics for Command, Address, Data Input, V Symbol Alt. Symbol t Address Latch Low to Write Enable High ALLWH t ALS t Address Latch High to Write Enable High ALHWH t Command Latch High to Write Enable High CLHWH t CLS t Command Latch Low to Write Enable High ...
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... Read Enable High to Output Hi-Z Read Enable Pulse Width Read Cycle time Read Enable Access time Read ES Access time Read Busy time Write Enable High to Ready/Busy Low Write Enable High to Read Enable Low Write Protection time NAND04GA3C2A, NAND04GW3C2A (1) 3V I/O Min 20 Min 20 Min 20 ...
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... NAND04GA3C2A, NAND04GW3C2A Figure 13. Command Latch AC Waveforms CL tCLHWH (CL Setup time) tELWH H(E Setup time tALLWH (ALSetup time) AL I/O Figure 14. Address Latch AC Waveforms CL tELWH (E Setup time) E tWLWH W tWHWL tALHWH (AL Setup time) tWHALL (AL Hold time) AL tDVWH (Data Setup time) Adrress I/O cycle 1 tWLWH tDVWH (Data Setup time) ...
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... Hold time) Data In 0 Data In 1 tRLRL (Read Cycle time) tRHRL (R High Holdtime) tRHQZ tRLQV Data Out Data Out NAND04GA3C2A, NAND04GW3C2A tWHCLH (CL Hold time) tWHEH (E Hold time) tWLWH tDVWH tWHDX tWHDX Data In Last tEHQZ tRHQZ tRLQV Data Out ...
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... NAND04GA3C2A, NAND04GW3C2A Figure 17. Read Status Register AC Waveform CL tCLHWH E tELWH W R (Data Setup time) I/O Figure 18. Read Electronic Signature AC Waveform I/O 90h Read Electronic Signature Command 1. Refer to Table 10 for the values of the Manufacturer and Device Codes, and to contained in Byte3 and Byte 4. tCLLRL ...
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... Command Address N Input Code 42/51 tWLWL tWHBL tALLRL2 tWHBH tRLRH tBLBH1 Data Add.N Add.N 30h cycle 4 N cycle 5 Busy from Address N to Last Byte or Word in Page NAND04GA3C2A, NAND04GW3C2A tEHQZ tRLRL tRHQZ (Read Cycle time) Data Data Data N+1 N+2 Last Data Output Ai11018b ...
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... NAND04GA3C2A, NAND04GW3C2A Figure 20. Page Program AC Waveform CL E tWLWL (Write Cycle time Add.N I/O 80h cycle1 RB Page Program Setup Code tWLWL Add.N Add.N Add.N Add.N N cycle 2 cycle 3 cycle 4 cycle 5 Address Input Data Input 12 DC and AC parameters tWLWL tWHBL tBLBH2 (Program Busy time) ...
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... RB Block Erase Block Address Input Setup Command Figure 22. Reset AC Waveform I/O FFh RB 44/51 tBLBH3 tWHBL (Erase Busy time) Add. Add. D0h cycle 2 cycle 3 Confirm Block Erase Code tWHBH1 (Reset Busy time) NAND04GA3C2A, NAND04GW3C2A 70h SR0 Read Status Register ai08043b ai08038c ...
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... NAND04GA3C2A, NAND04GW3C2A Figure 23. Program/Erase Enable Waveform W tVHWH WP RB I/O Figure 24. Program/Erase Disable Waveform W tVLWH WP High RB I/O 80h 80h 12 DC and AC parameters 10h ai12709 10h ai12710 45/51 ...
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... P ( – V DDmax V OLmax = ------------------------------------------------------------- R P min + I OL 1.85V ( ) = -------------------------- - R P min 1.8V 3mA 3. -------------------------- - R P min 3V + 8mA . r ready DEVICE V SS NAND04GA3C2A, NAND04GW3C2A ) busy t r AI07564B ibusy Open Drain Output AI07563B P ...
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... NAND04GA3C2A, NAND04GW3C2A Figure 27. Resistor Value Versus Waveform Timings For Ready/Busy Signal V DDQ = 1.8V 30pF 400 300 200 1.7 100 0. 1.7 1 25°C. 4 400 3 300 2.4 2 200 120 1 100 100 90 0.57 0.43 3.6 1.7 1 and AC parameters V DDQ = 3.3V 100pF 400 ...
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... NAND04GA3C2A, NAND04GW3C2A TSOP-G inches Typ Min 0.0039 0.0020 0.0394 0.0374 0.0087 0.0067 0.0039 0.4724 0.4685 0.7874 0.7795 ...
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... NAND04GA3C2A, NAND04GW3C2A 14 Part numbering Table 22. Ordering Information Scheme Example: Device Type NAND Flash Memory Density 04G = 4Gb Operating Voltage 2.7 to 3.6V DDQ 1.7V to 1.95V DDQ Bus Width Family Identifier C = 2112 Bytes Page MLC Device Options 2 = Chip Enable Don't Care Enabled Product Version ...
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... Revision history 15 Revision history Table 23. Document revision history Date 16-Mar-2006 09-Nov-2006 50/51 Revision 1 Initial release. NAND08GA2C2A and NAND08GW2C2A root part numbers 2 removed. NAND04GA3C2A, NAND04GW3C2A Changes ...
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... NAND04GA3C2A, NAND04GW3C2A Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...