HYB39S256160FE-6 QIMONDA [Qimonda AG], HYB39S256160FE-6 Datasheet
HYB39S256160FE-6
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HYB39S256160FE-6 Summary of contents
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HY[B/I]39S256[40/80/16]0FT(L), HY[B/I]39S256[40/80/16]0FE(L), HYB39S256[40/80/16]0FF(L), HYB39S256407FE Revision History: 2007-09, Rev. 1.42 Page Subjects (major changes since last revision) All Adapted internet edition 7 Corrected SDRAM organization for x4 in Table 4 Previous Revision: 2007-09, Rev. 1.41 All Editorial Change 4 Corrected HYB39S256407FF-7 ...
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Overview This chapter lists all main features of the product family HYB39S256[400/800/160]F[E/T/F](L) and the ordering information. 1.1 Features • Fully Synchronous to Positive Clock Edge • °C Standard Operating Temperature • - °C Industrial ...
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... HYB39S256800FE-7 HYB39S256800FFL-7 HYB39S256800FEL-7 HYB39S256160FF-7 HYB39S256160FE-7 HYB39S256160FFL-7 HYB39S256160FEL-7 HYB39S256160FF-6 HYB39S256160FE-6 HYB39S256160FFL-6 HYB39S256160FEL-6 Industrial Operating Temperature HYI39S256800FE-7 PC166-333 HYI39S256160FE-7 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers ...
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Product Type Speed Grade Standard Operating Temperature HYB39S256400FT-7 PC133-222 HYB39S256400FTL-7 HYB39S256800FT-7 HYB39S256800FTL-7 HYB39S256160FT-7 HYB39S256160FTL-7 HYB39S256160FT-6 Industrial Operating Temperature HYI39S256800FT-7 PC133-222 HYI39S256160FT-7 Note: For product nomenclature see Chapter 6 Rev. 1.42, 2007-09 03292006-TMTK-JFEU HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L) Ordering Information for Lead-Containing Products Description 143MHz ...
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Configuration This chapter contains the pin configuration table, the TSOP and FBGA package drawing, and the block diagrams for the ×4, ×8, ×16 organization of the SDRAM. 2.1 Pin Description Listed below are the pin configurations sections for the ...
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Ball No. Name Pin Buffer Type Type Data Signals ×4 Organization 5, 8B DQ0 I/O LVTTL 11, 8D DQ1 I/O LVTTL 44, 2D DQ2 I/O LVTTL 50, 2B DQ3 I/O LVTTL Data Signals ×8 Organization 2, 8A DQ0 I/O LVTTL ...
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Ball No. Name Pin Buffer Type Type V 7E, 9A, PWR – 3A, 3C, PWR – SSQ 7B 1J, 1A, PWR – Not connected ×4 Organization – ...
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Package P(G)–TSOPII–54 Listed below are the pin outs of the TSOP package. Rev. 1.42, 2007-09 03292006-TMTK-JFEU HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L) 256-MBit Synchronous DRAM Pinouts P(G)–TSOPII–54 9 Internet Data Sheet FIGURE 1 ...
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Package PG–TFBGA–54 Listed below are the ball outs of the TFBGA package. Figure 2 “Ballout for ×16 components, TFBGA-54 (top view)” on Page 10 • Figure 3 “Ballout for ×8 components, TFBGA-54 (top view)” on Page 11 • Figure ...
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Rev. 1.42, 2007-09 03292006-TMTK-JFEU HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L) 256-MBit Synchronous DRAM Ballout for ×8 components, TFBGA-54 (top view) 11 Internet Data Sheet FIGURE 3 ...
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Rev. 1.42, 2007-09 03292006-TMTK-JFEU HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L) 256-MBit Synchronous DRAM Ballout for ×4 components, TFBGA-54 (top view) 12 Internet Data Sheet FIGURE 4 ...
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Functional Description This chapter contains the functional description. Operation Device State 3) Bank Active Idle Bank Precharge Any Precharge All Any 3) Write Active 3) Write with Auto pre- Active charge 3) Read Active 3) Read with Auto pre- ...
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Field Bits Type BL 2 6:4 TM 8:7 WBL 9 12:10 Rev. 1.42, 2007-09 03292006-TMTK-JFEU HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L) Mode Register Definition (BA Description Burst Length Note: All other bit combinations are RESERVED 000 1 B 001 2 B ...
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Burst Length Starting Column Address FullPage n Notes 1. For a burst length of two, ...
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Electrical Characteristics This chapter lists the electrical characteristics. 4.1 Operating Conditions This chapter describes the operating conditions. Parameter V Input / Output voltage relative Voltage on supply relative Voltage on ...
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Parameter Supply Voltage I/O Supply Voltage Input high voltage Input low voltage I Output high voltage ( = – 4.0 mA) OUT I Output low voltage ( = 4.0 mA) OUT Input leakage current, any input (0 V < Output ...
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Parameter Self Refresh Current (standard components) t Self Refresh Mode, CKE=0.2V, =infinity CK Self Refresh Current (low power components) t Self Refresh Mode, CKE=0.2V, =infinity CK Symbol DD1 RC RC(min) O ...
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AC Characteristics This chapter lists the AC characteristics. Parameter Clock and Clock Enable Clock Frequency Access Time from Clock Clock High Pulse Width Clock Low Pulse Width Transition time Setup and Hold Times Input Setup Time Input Hold Time ...
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Parameter Write Cycle Last Data Input to Precharge (Write without Auto Precharge) Last Data Input to Activate(Write with Auto Precharge) DQM Write Mask Latency ° 3.3 ...
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Package Outlines This chapter contains the package outlines of the products. Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.42, 2007-09 03292006-TMTK-JFEU HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L) 256-MBit Synchronous DRAM Package Outline P(G)-TSOPII-54 (top ...
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Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.42, 2007-09 03292006-TMTK-JFEU HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L) 256-MBit Synchronous DRAM Package Outline P(G)-TFBGA-54 22 Internet Data Sheet FIGURE 7 ...
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... S 256 256 16 0 Values Coding HYB Memory components HYI Memory components, industrial temperature range (-40°C – +85 ° Single Data Rate SDRAM 128 128 Mbit 256 256 Mbit 512 512 Mbit ×4 40 ×8 80 × look up table ...
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List of Figures Figure 1 Pinouts P(G)–TSOPII– ...
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... Table 9 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 10 Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 11 IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 I Table 12 Specifications and Conditions Table 13 AC Timing - Absolute Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 14 Examples for Nomenclature Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 15 Memory Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Rev. 1.42, 2007-09 03292006-TMTK-JFEU HY[B/I]39S256[40/80/16][0/7]F[E/T/F]( 1 Internet Data Sheet 256-MBit Synchronous DRAM ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Edition 2007-09 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or ...