HYB39S256400T-10

Manufacturer Part NumberHYB39S256400T-10
Description256 MBit Synchronous DRAM
ManufacturerSIEMENS [Siemens Semiconductor Group]
HYB39S256400T-10 datasheet
 
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256 MBit Synchronous DRAM
Preliminary Information
• High Performance:
-8
-8B
-10
f
125
100
100
CK
t
8
10
10
CK3
t
6
6
7
AC3
t
10
12
15
CK2
t
6
7
8
AC2
• Fully Synchronous to Positive Clock Edge
• 0 to 70 C operating temperature
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2, 3, 4
• Programmable Wrap Sequence: Sequential
or Interleave
• Programmable Burst Length:
1, 2, 4, 8
The
HYB 39S256400/800/160T
4 banks
16 MBit 4, 4 banks
chronous devices achieve high speed data transfer rates for CAS latencies by employing a chip
architecture that prefetches multiple bits and then synchronizes the output data to a system clock.
The chip is fabricated with SIEMENS’ advanced 256 MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3 V
0.3 V power supply and are available in TSOPII packages.
Semiconductor Group
• Multiple Burst Read with Single Write
Operation
Units
• Automatic and Controlled Precharge
MHz
Command
ns
• Data Mask for Read/Write control ( 4, 8)
• Data Mask for byte control ( 16)
ns
• Auto Refresh (CBR) and Self Refresh
ns
• Suspend Mode and Power Down Mode
ns
• 8192 refresh cycles/64 ms 7,8
• Random Column Address every CLK
(1-N Rule)
• Single 3.3 V
• LVTTL Interface versions
• Plastic Packages:
P-TSOPII-54 400mil width ( 4, 8, 16)
• -8 part for PC100 2-2-2 operation
-8B part for PC100 3-2-3 operation
-10 part for PC66 2-2-2 operation
are
four
bank
Synchronous
8 MBit 8 and 4 banks
1
HYB 39S256400/800/160T
0.3 V Power Supply
DRAM’s
organized
4 MBit 16 respectively. These syn-
1998-10-01
as