HYB39S256400T-10 SIEMENS [Siemens Semiconductor Group], HYB39S256400T-10 Datasheet

HYB39S256400T-10

Manufacturer Part Number

HYB39S256400T-10

Description

256 MBit Synchronous DRAM

Manufacturer

SIEMENS [Siemens Semiconductor Group]

Datasheet

1.HYB39S256400T-10.pdf (56 pages)

Current page: 1 of 56
Download datasheet (407Kb)

256 MBit Synchronous DRAM

Preliminary Information

• High Performance:

• Fully Synchronous to Positive Clock Edge

• 0 to 70 C operating temperature

• Four Banks controlled by BA0 & BA1

• Programmable CAS Latency: 2, 3, 4

• Programmable Wrap Sequence: Sequential

• Programmable Burst Length:

The

4 banks

chronous devices achieve high speed data transfer rates for CAS latencies by employing a chip

architecture that prefetches multiple bits and then synchronizes the output data to a system clock.

The chip is fabricated with SIEMENS’ advanced 256 MBit DRAM process technology.

The device is designed to comply with all JEDEC standards set for synchronous DRAM products,

both electrically and mechanically. All of the control, address, data input and output circuits are

synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleave fashion allows random access operation to occur

at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of is

possible depending on burst length, CAS latency and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a

single 3.3 V

Semiconductor Group

or Interleave

1, 2, 4, 8

CK3

AC3

CK2

AC2

HYB 39S256400/800/160T

16 MBit 4, 4 banks

125

-8

0.3 V power supply and are available in TSOPII packages.

100

-8B

100

-10

Units

MHz

8 MBit 8 and 4 banks

are

four

bank

• Multiple Burst Read with Single Write

• Automatic and Controlled Precharge

• Data Mask for Read/Write control ( 4, 8)

• Data Mask for byte control ( 16)

• Auto Refresh (CBR) and Self Refresh

• Suspend Mode and Power Down Mode

• 8192 refresh cycles/64 ms 7,8

• Random Column Address every CLK

• Single 3.3 V

• LVTTL Interface versions

• Plastic Packages:

• -8 part for PC100 2-2-2 operation

Operation

Command

(1-N Rule)

P-TSOPII-54 400mil width ( 4, 8, 16)

-8B part for PC100 3-2-3 operation

-10 part for PC66 2-2-2 operation

Synchronous

4 MBit 16 respectively. These syn-

HYB 39S256400/800/160T

0.3 V Power Supply

DRAM’s

organized

1998-10-01

Related parts for HYB39S256400T-10

Related keywords

HYB39S256400T-10 datasheet
HYB39S256400T-10 data sheet
HYB39S256400T-10 pdf datasheet
HYB39S256400T-10 component
HYB39S256400T-10 part
HYB39S256400T-10 distributor
HYB39S256400T-10 RoHS
HYB39S256400T-10 datasheet download