HYB39S256400T-10 SIEMENS [Siemens Semiconductor Group], HYB39S256400T-10 Datasheet - Page 13

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HYB39S256400T-10

Manufacturer Part Number
HYB39S256400T-10
Description
256 MBit Synchronous DRAM
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
HYB 39S256400/800/160T
256 MBit Synchronous DRAM
The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when RAS,
CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the
clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation.
After the exit command, at least one
t
delay is required prior to any access command.
RC
DQM Function
DQM has two functions for data I/O read and write operations. During reads, when it turns to “high”
at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM
t
Data Disable Latency
). It also provides a data mask function for writes. When DQM is activated,
DQZ
the write operation at the next clock is prohibited (DQM Write Mask Latency
t
= zero clocks).
DQW
Suspend Mode
During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the
internal clock and extends data read and write operations. One clock delay is required for mode
t
entry and exit (Clock Suspend Latency
).
CSL
Power Down
In order to reduce standby power consumption, a power down mode is available. All banks must be
t
precharged and the necessary Precharge delay (
) must occur before the SDRAM can enter the
RP
Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the receiver
circuits except CLK and CKE are gated off. The Power Down mode does not perform any refresh
operations, therefore the device can’t remain in Power Down mode longer than the Refresh period
t
(
) of the device. Exit from this mode is performed by taking CKE “high“. One clock delay is
REF
required for mode entry and exit.
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge
function is initiated. The SDRAM automatically enters the precharge operation one clock before the
last data out for CAS latencies 2, two clocks for CAS latencies 3 and three clocks for CAS
latencies 4. If CAS10 is high when a Write Command is issued, the Write with Auto-Precharge
function is initiated. The SDRAM automatically enters the precharge operation a time delay equal to
t
(Write recovery time) after the last data in.
WR
Precharge Command
There is also a separate precharge command available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are
used to define banks as shown in the following list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2, two clocks before the last data out for
CAS latency = 3 and three clocks before the last data out for CAS latency = 4. Writes require a time
t
delay
from the last data out to apply the precharge command.
WR
Semiconductor Group
13
1998-10-01

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