HYB39S256400T-10 SIEMENS [Siemens Semiconductor Group], HYB39S256400T-10 Datasheet - Page 7

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HYB39S256400T-10

Manufacturer Part Number
HYB39S256400T-10
Description
256 MBit Synchronous DRAM
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
Signal Pin Description
Pin
CLK
CKE
CS
RAS
CAS
WE
A0 -
A12
BA0
BA1
DQx
Semiconductor Group
Type
Input
Input
Input
Input
Input
Input
Input
Out-
put
Signal Polarity Function
Pulse
Level
Pulse
Pulse
Level
Level
Level
Positive
Edge
Active
High
Active
Low
Active
Low
The system clock input. All of the SDRAM inputs are
sampled on the rising edge of the clock.
Activates the CLK signal when high and deactivates the CLK
signal when low, thereby initiates either the Power Down
mode, Suspend mode, or the Self Refresh mode.
CS enables the command decoder when low and disables
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.
When sampled at the positive rising edge of the clock, CAS,
RAS, and WE define the command to be executed by the
SDRAM.
During a Bank Activate command cycle, A0 - A12 defines the
row address (RA0 - RA12) when sampled at the rising clock
edge.
During a Read or Write command cycle, A0 - An defines the
column address (CA0 - CAn) when sampled at the rising
clock edge. CAn depends from the SDRAM organization:
64M
32M
16M
In addition to the column address, A10 (= AP) is used to
invoke autoprecharge operation at the end of the burst read
or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in
conjunction with BA0 and BA1 to control which bank(s) to
precharge. If A10 is high, all four banks will be precharged
regardless of the state of BA0 and BA1. If A10 is low, then
BA0 and BA1 are used to define which bank to precharge.
Bank Select (BS) Inputs. Selects which bank is to be active.
Data Input/Output pins operate in the same manner as on
conventional DRAMs.
4 SDRAM CAn = CA9, CA11
8 SDRAM CAn = CA9
16 SDRAM CAn = CA8
7
256 MBit Synchronous DRAM
HYB 39S256400/800/160T
(Page Length = 2048 bits)
(Page Length = 1024 bits)
(Page Length = 512 bits)
1998-10-01

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