HYB39S64160AT-10 SIEMENS [Siemens Semiconductor Group], HYB39S64160AT-10 Datasheet

HYB39S64160AT-10

Manufacturer Part Number

HYB39S64160AT-10

Description

64 MBit Synchronous DRAM

Manufacturer

SIEMENS [Siemens Semiconductor Group]

Datasheet

1.HYB39S64160AT-10.pdf (53 pages)

Current page: 1 of 53
Download datasheet (677Kb)

64 MBit Synchronous DRAM

•

The HYB39S64400/800/160AT are four bank Synchronous DRAM’s organized as 4 banks x 4MBit

x4, 4 banks x 2MBit x8 and 4 banks x 1Mbit x16 respectively. These synchronous devices achieve

high speed data transfer rates by employing a chip architecture that prefetches multiple bits and

then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS’

advanced quarter micron 64MBit DRAM process technology.

The device is designed to comply with all JEDEC standards set for synchronous DRAM products,

both electrically and mechanically. All of the control, address, data input and output circuits are

synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleave fashion allows random access operation to occur

at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible

depending on burst length, CAS latency and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a

single 3.3V +/- 0.3V power supply and are available in TSOPII packages.

The -8 version of this product is best suited for use on a 100 Mhz bus for both CAS latencies 2 & 3.

Semiconductor Group

fCK

High Performance:

Fully Synchronous to Positive Clock Edge

0 to 70 C operating temperature

Four Banks controlled by BA0 & BA1

Programmable CAS Latency: 2 & 3

Programmable Wrap Sequence: Sequential

or Interleave

Programmable Burst Length: 1, 2, 4, 8

full page (optional) for sequential wrap

around

tCK3

tAC3

tCK2

tAC2

max.

125

-8

100

-8B

100

-10

Units

MHz

•

Multiple Burst Read with Single Write

Operation

Automatic

Command

Data Mask for Read / Write control (x4, x8)

Data Mask for byte control (x16)

Auto Refresh (CBR) and Self Refresh

Suspend Mode and Power Down Mode

4096 refresh cycles / 64 ms

Random Column Address every CLK

( 1-N Rule)

Single 3.3V +/- 0.3V Power Supply

LVTTL Interface version

Plastic Packages:

P-TSOPII-54 400mil width (x4, x8, x16)

-8 version for PC100 2-2-2 applications

-8B version for PC100 3-2-3 applications

64MBit Synchronous DRAM

HYB39S64400/800/160AT(L)

and

Controlled

Precharge

10.98

Related parts for HYB39S64160AT-10

Related keywords

HYB39S64160AT-10 datasheet
HYB39S64160AT-10 data sheet
HYB39S64160AT-10 pdf datasheet
HYB39S64160AT-10 component
HYB39S64160AT-10 part
HYB39S64160AT-10 distributor
HYB39S64160AT-10 RoHS
HYB39S64160AT-10 datasheet download