M58BW016BB100T3T

Manufacturer Part NumberM58BW016BB100T3T
Description16 Mbit 512Kb x32, Boot Block, Burst 3V Supply Flash Memories
ManufacturerSTMICROELECTRONICS [STMicroelectronics]
M58BW016BB100T3T datasheet
 
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PE4FEATURES SUMMARY
SUPPLY VOLTAGE
– V
= 2.7V to 3.6V for Program, Erase and
DD
Read
– V
= V
= 2.4V to 3.6V for I/O Buffers
DDQ
DDQIN
– V
= 12V for fast Program (optional)
PP
HIGH PERFORMANCE
– Access Time: 80, 90 and 100ns
– 56MHz Effective Zero Wait-State Burst Read
– Synchronous Burst Reads
– Asynchronous Page Reads
HARDWARE BLOCK PROTECTION
– WP pin Lock Program and Erase
SOFTWARE BLOCK PROTECTION
– Tuning Protection to Lock Program and
Erase with 64 bit User Programmable Pass-
word (M58BW016B version only)
OPTIMIZED for FDI DRIVERS
– Fast Program / Erase suspend latency
time < 6µs
– Common Flash Interface
MEMORY BLOCKS
– 8 Parameters Blocks (Top or Bottom)
– 31 Main Blocks
LOW POWER CONSUMPTION
– 5µA Typical Deep Power Down
– 60µA Typical Standby
– Automatic Standby after Asynchronous Read
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code M58BW016xT: 8836h
– Bottom Device Code M58BW016xB: 8835h
May 2003
M58BW016BT, M58BW016BB
M58BW016DT, M58BW016DB
16 Mbit (512Kb x32, Boot Block, Burst)
3V Supply Flash Memories
Figure 1. Packages
PQFP80 (T)
BGA
LBGA80 (ZA)
10 x 8 ball array
1/63

M58BW016BB100T3T Summary of contents

  • Page 1

    ... OPTIMIZED for FDI DRIVERS – Fast Program / Erase suspend latency time < 6µs – Common Flash Interface MEMORY BLOCKS – 8 Parameters Blocks (Top or Bottom) – 31 Main Blocks LOW POWER CONSUMPTION – 5µA Typical Deep Power Down – 60µA Typical Standby – ...

  • Page 2

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 3

    ... Valid Clock Edge Bit (M6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Wrap Burst Bit (M3 Burst Length Bit (M2-M0 Table 7. Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Read Memory Array Command Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Read Query Command Read Status Register Command Clear Status Register Command Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Program Command ...

  • Page 4

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 5

    Figure 26. Unlock Device and Program a Tuning Protected Block Flowchart . . . . . . . . . . . . . . . . 54 Figure 27. Unlock Device and Erase a Tuning Protected Block Flowchart . ...

  • Page 6

    ... Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are re- quired to update the memory contents. The end of a Program or Erase operation can be detected and any error conditions identified in the Status Regis- 6/63 ter ...

  • Page 7

    Figure 2. Logic Diagram DDQ V DDQIN A0-A18 K L M58BW016BT E M58BW016BB RP M58BW016DT M58BW016DB SSQ M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Table 1. Signal Names A0-A18 DQ0-DQ7 V PP ...

  • Page 8

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 3. LBGA Connections (Top view through package A15 A14 B A16 A13 C A17 A18 D DQ3 DQ0 E V DDQ DQ4 F V SSQ DQ7 G V DDQ DQ8 H DQ13 DQ12 ...

  • Page 9

    Figure 4. PQFP Connections (Top view through package) DQ16 DQ17 DQ18 DQ19 V DDQ V SSQ DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 12 DQ26 DQ27 V DDQ V SSQ DQ28 DQ29 DQ30 DQ31 M58BW016BT, M58BW016BB, ...

  • Page 10

    ... The code is written once in the Tuning Protection Register and cannot be erased. When shipped the , IL flash memory will have the Tuning Protection Code bits set to ‘1'. The user can program a ‘0’ in any of the 64 positions. Once programmed it is not ) all the possible to reset a bit to ‘1’ as the cells cannot be IH erased ...

  • Page 11

    Table 2. Top Boot Block Addresses, M58BW016BT, M58BW016DT # Size (Kbit) Address Range 38 64 7F800h-7FFFFh 37 64 7F000h-7F7FFh 36 64 7E800h-7EFFFh 35 64 7E000h-7E7FFh 34 64 7D800h-7DFFFh 33 64 7D000h-7D7FFh 32 64 7C800h-7CFFFh 31 64 7C000h-7C7FFh 30 512 78000h-7BFFFh ...

  • Page 12

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Table 3. Bottom Boot Block Addresses, M58BW016BB, M58BW016DB # Size (Kbit) Address Range 38 512 7C000h-7FFFFh 37 512 78000h-7BFFFh 36 512 74000h-77FFFh 35 512 70000h-73FFFh 34 512 6C000h-6FFFFh 33 512 68000h-6BFFFh 32 512 64000h-67FFFh 31 512 ...

  • Page 13

    ... The device acts as deselected, that is . The ad- the data outputs are high impedance. IL After Reset/Power-Down goes High, V memory will be ready for Bus Read operations af- ter a delay PHWL If Reset/Power-Down goes low, V Erase, a Program or a Tuning Protection Program the operation is aborted time of t mum, and data is altered and may be corrupted ...

  • Page 14

    ... Valid Data Ready (R). The Valid Data Ready output open drain output that can be used, during Synchronous Burst Read operations, to identify if the memory is ready to output data or not. The Valid Data Ready output can be config- ured to be active on the clock edge of the invalid data read cycle or one cycle before ...

  • Page 15

    ... Waveforms and Table 18, Asynchronous Page Read AC Characteristics for details on when the outputs become valid. Asynchronous Bus Write. Asynchronous Write operations write to the Command Interface in order to send commands to the memory Chip Enable IL latch addresses and input data to program. Bus Write operations are asynchronous, the clock don’ ...

  • Page 16

    ... The Electronic IH Signature is output by giving the Read Electronic Signature command. The manufacturer code is output when all the Address inputs are at V device code is output when other address pins are Read Memory Array command to return to Read mode. Step ...

  • Page 17

    ... When Valid Data Ready is Low on the active clock edge, no new data is available and the memory does not increment the internal address counter at the active clock edge even if Burst Address Ad- vance Low. Valid Data Ready may be configured (by bit M8 of ...

  • Page 18

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Table 6. Synchronous Burst Read Bus Operations Bus Operation Address Latch Read Read Suspend Synchronous Burst Read Read Resume Burst Address Advance Read Abort, E Read Abort, RP Note Don't Care ...

  • Page 19

    ... Burst Configuration Register The Burst Configuration Register is used to config- ure the type of bus access that the memory will perform. The Burst Configuration Register is set through the Command Interface and will retain its informa- tion until it is re-configured, the device is reset, or the device goes into Reset/Power-Down mode. ...

  • Page 20

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Table 7. Burst Configuration Register Bit Description M15 Read Select M14 (2) M13-M11 X-Latency M10 (3) M9 Y-Latency M8 Valid Data Ready M7 Burst Type M6 Valid Clock Edge M5-M4 M3 Wrapping M2-M0 Burst Length Note: ...

  • Page 21

    Table 8. Burst Type Definition Starting Address Sequential Interleaved 0 0 0-1-2 1-2-3 2-3-0 3-0-1 – – – – – 1 ...

  • Page 22

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 5. Example Burst Configuration X-1-1 ADD VALID L DQ 4-1-1-1 DQ 5-1-1-1 DQ 6-1-1-1 DQ 7-1-1-1 DQ 8-1-1-1 Figure 6. Example Burst Configuration X-2-2 ADD VALID L DQ 5-2-2-2 ...

  • Page 23

    ... Read Memory Array Command The Read Memory Array command returns the memory to Read mode. One Bus Write cycle is re- quired to issue the Read Memory Array command and return the memory to Read mode. Subse- quent read operations will output the addressed memory array data ...

  • Page 24

    ... Block Erase command. Program Command. The Program command is used to program the memory array. Two Bus Write operations are re- quired to issue the command; the first write cycle sets up the Program command, the second write cycle latches the address and data to be pro- grammed in the internal state machine and starts the Program/Erase Controller ...

  • Page 25

    ... The second cycle writes the Burst Configuration Register data and the confirm com- mand. Once the command is issued the memory returns to Read mode Read Memory Array command had been issued. The value for the Burst Configuration Register is always presented on A0-A15 A0 A1, etc. ...

  • Page 26

    ... Programming aborts if V drops out of the al- PP lowed range or RP goes Read Memory Array command must be issued to return the memory to read mode before issuing Table 9. Commands Command Read Memory Array 2 Write Read Electronic Signature 2 Write (Manufacturer Code) ...

  • Page 27

    Table 10. Program, Erase Times and Program Erase Endurance Cycles Parameters Parameter Block (64Kb) Program Main Block (512Kb) Program Parameter Block Erase Main Block Erase Program Suspend Latency Time Erase Suspend Latency Time Program/Erase Cycles (per Block) Note ...

  • Page 28

    ... The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Erase Status bit is set to ‘0’, the memory has successfully verified that the block has erased correctly. When the Erase Status bit is set to ‘1’, ...

  • Page 29

    ... Program/Erase Controller is active or has com- pleted its operation; when the bit is set to ‘1’, a Pro- gram/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is is- sued the Program Suspend Status bit returns to ‘ ...

  • Page 30

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB MAXIMUM RATING Stressing the device above the ratings listed in Ta- ble 12, Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or ...

  • Page 31

    DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC characteristics Tables that follow, are de- rived from tests performed ...

  • Page 32

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Table 15. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Supply Current (Random Read Supply Current (Burst Read) DDB Supply Current (Standby) I DD1 Supply Current (Auto ...

  • Page 33

    Figure 9. Asynchronous Bus Read AC Waveforms A0-A18 A0-A18 DQ0-DQ31 DQ0-DQ31 Table 16. Asynchronous Bus Read AC Characteristics. Symbol Parameter t Address Valid to Address Valid AVAV t Address Valid to Output ...

  • Page 34

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 10. Asynchronous Latch Controlled Bus Read AC Waveforms A0-A18 tAVLL L tLHLL E G DQ0-DQ31 Table 17. Asynchronous Latch Controlled Bus Read AC Characteristics Symbol Parameter t Address Valid to Latch Enable Low AVLL t ...

  • Page 35

    Figure 11. Asynchronous Page Read AC Waveforms A0-A1 DQ0-DQ31 Table 18. Asynchronous Page Read AC Characteristics Symbol Parameter t Address Valid to Output Valid AVQV1 t Address Transition to Output Transition AXQX Note: For other timings see Table 16, Asynchronous ...

  • Page 36

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 12. Asynchronous Write AC Waveform 36/63 ...

  • Page 37

    Figure 13. Asynchronous Latch Controlled Write AC Waveform M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB 37/63 ...

  • Page 38

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics Symbol Parameter t Address Valid to Latch Enable Low AVLL t Address Valid to Write Enable High AVWH t Data Input Valid to Write Enable High ...

  • Page 39

    Figure 14. Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge) M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB 39/63 ...

  • Page 40

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Table 20. Synchronous Burst Read AC Characteristics Symbol Parameter t Address Valid to Latch Enable Low AVLL Burst Address Advance High to Valid Clock t BHKH Edge Burst Address Advance Low to Valid Clock t BLKH ...

  • Page 41

    ... open drain output with an internal pull up resistor of 1M 300k for a single memory on the R bus, should be used to give the data valid set up time required to recognize that valid data is available on the next valid clock edge. Figure 17. Synchronous Burst Read - Burst Address Advance ...

  • Page 42

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 18. Reset, Power-Down and Power-up AC Waveform tVDHPH VDD, VDDQ Table 21. Reset, Power-Down and Power-up AC Characteristics Symbol t Reset/Power-down High to Chip Enable Low PHEL (1) Reset/Power-down High ...

  • Page 43

    PACKAGE MECHANICAL Figure 19. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Bottom View Package Outline BALL "A1" Note: Drawing is not to scale. Table 22. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Package Mechanical ...

  • Page 44

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 20. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline QFP-B Note: Drawing is not to scale. Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data Symbol ...

  • Page 45

    ... Option T = Tape & Reel Packing Note: Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de- vice, please contact the ST Sales Office nearest to you. ...

  • Page 46

    ... APPENDIX A. COMMON FLASH INTERFACE - CFI The Common Flash Interface is a JEDEC ap- proved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory ...

  • Page 47

    ... Not Available Data n 15h 2 number of bytes memory size 03h Device Interface Sync./Async. 00h Organization Sync./Async. 00h n Page size in bytes, 2 00h 02h Bit7-0 = number of Erase Block Regions in device 1Eh Number (n-1) of blocks of identical size ...

  • Page 48

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Table 29. Extended Query information Address Address offset A18-A0 (P)h 35h (P+1)h 36h (P+2)h 37h (P+3)h 38h (P+4)h 39h (P+5)h 3Ah (P+6)h 3Bh (P+7)h 3Ch (P+8)h 3Dh (P+9)h 3Eh (P+A)h 3Fh Note: 1. Not supported. 48/63 ...

  • Page 49

    ... Error (1) NO Program to Protect Block Error Program Command: – write 40h – write Address & Data (memory enters read status state after the Program command) do: – read status register ( must be toggled) while invalid error: – error handler Program error: – ...

  • Page 50

    ... Program/Erase Suspend Command: – write B0h – write 70h do: – read status register while Program completed Read Memory Array Command: – write FFh – one or more data reads from other blocks Program Erase Resume Command: – write D0h to resume erasure – ...

  • Page 51

    ... Error (1) NO Erase to Protected Block Error Erase Command: – write 20h – write Block Address (A11-A18) & D0h (memory enters read status state after the Erase command) do: – read status register ( must be toggled) if Erase command given execute suspend erase loop while invalid error: – ...

  • Page 52

    ... Program/Erase Suspend Command: – write B0h – write 70h do: – read status register while Erase completed Read Memory Array command: – write FFh – one or more data reads from other blocks Program/Erase Resume command: – write D0h to resume the Erase operation – ...

  • Page 53

    Figure 25. Unlock Device and Change Tuning Protection Code Flowchart Reset Device locked by tuning code Add: don't care Data: 0x78h Add: 0x00000h Data: First 32 bit Add: don't care Data: 0xFFh Issue Read command Add: don't ...

  • Page 54

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 26. Unlock Device and Program a Tuning Protected Block Flowchart Reset Device locked by tuning code Add: don't care Data: 0x78h Add: 0x00000h Data: First 32 bit Add: don't care Data: 0xFFh ...

  • Page 55

    Figure 27. Unlock Device and Erase a Tuning Protected Block Flowchart Reset Device locked by tuning code Add: don't care Data: 0x78h Add: 0x00000h Data: First 32 bit Add: don't care Data: 0xFFh Issue Read command Add: ...

  • Page 56

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 28. Power-up Sequence to Burst the Flash Power-up or Reset Asynchronous Read Write 60h command Write 03h with A15-A0 BCR inputs Synchronous Read 56/63 BCR bit 15 = '1' Set Burst Configuration Register Command: – ...

  • Page 57

    Figure 29. Command Interface and Program Erase Controller Flowchart (a) WAIT FOR COMMAND WRITE NO 90h YES READ ELEC. 98h SIGNATURE READ CFI ERASE COMMAND ERROR READ STATUS B M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB NO YES NO 70h YES READ NO ...

  • Page 58

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 30. Command Interface and Program Erase Controller Flowchart ( 48h YES TP 78h PROGRAM SET_UP F TP UNLOCK SET_UP G 58/63 NO YES NO 60h YES NO FFh SET BCR SET_UP YES NO ...

  • Page 59

    Figure 31. Command Interface and Program Erase Controller Flowchart (c) B READ STATUS READ ARRAY M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB NO ERASE SUSPENDED YES YES 70h NO YES PROGRAM 40h SET_UP NO NO YES READ D0h STATUS A ERASE YES READY ...

  • Page 60

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 32. Command Interface and Program Erase Controller Flowchart ( READ STATUS READ ARRAY 60/63 PROGRAM SUSPENDED YES YES 70h NO NO YES READ D0h STATUS C PROGRAM YES READY NO NO READ B0h ...

  • Page 61

    Figure 33. Command Interface and Program Erase Controller Flowchart (e) M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB PROGRAM YES NO READY UNLOCK YES NO READY READ STATUS READ STATUS AI03839 61/63 ...

  • Page 62

    M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB REVISION HISTORY Table 30. Document Revision History Date Version January-2001 -01 05-Jun-2001 -02 15-Jun-2001 -03 17-Jul-2001 -04 17-Dec-2001 -05 17-Jan-2002 -06 30-Aug-2002 6.1 4-Sep-2002 7.0 13-May-2003 7.1 62/63 Revision Details First Issue. Major rewrite and restructure. ...

  • Page 63

    Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. ...