M58BW016BB100T3T STMICROELECTRONICS [STMicroelectronics], M58BW016BB100T3T Datasheet - Page 14

• Manufacturer Part Number: M58BW016BB100T3T
• Description: 16 Mbit 512Kb x32, Boot Block, Burst 3V Supply Flash Memories
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
ing Synchronous Burst Read operations. Bus sig-
nals are latched on the active edge of the Clock.
The Clock can be configured to have an active ris-
ing or falling edge. In Synchronous Burst Read
mode the address is latched on the first active
clock edge when Latch Enable is low, V
the rising edge of Latch Enable, whichever occurs
first.
During Asynchronous bus operations the Clock is
not used.
Burst Address Advance (B). The Burst Address
Advance, B, controls the advancing of the address
by the internal address counter during Synchro-
nous Burst Read operations.
Burst Address Advance, B, is only sampled on the
active clock edge of the Clock when the X-latency
time has expired. If Burst Address Advance is
Low, V
Burst Address Advance is High, V
address counter does not change; the same data
remains on the Data Inputs/Outputs and Burst Ad-
dress Advance is not sampled until the Y-latency
expires.
The Burst Address Advance, B, may be tied to V
Valid Data Ready (R). The Valid Data Ready
output, R, is an open drain output that can be
used, during Synchronous Burst Read operations,
to identify if the memory is ready to output data or
not. The Valid Data Ready output can be config-
ured to be active on the clock edge of the invalid
data read cycle or one cycle before. Valid Data
Ready, at V
available. When Valid Data Ready is Low, V
previous data outputs remain active.
In all Asynchronous operations, Valid Data Ready
is high-impedance. It may be tied to other compo-
nents with the same Valid Data Ready signal to
create a unique system Ready signal. The Valid
Data Ready output has an internal pull-up resistor
of around 1 M
should use an external pull-up resistor of the cor-
rect value to meet the external timing require-
ments for Valid Data Ready going to V
Write Protect (WP). The Write Protect, WP, pro-
vides protection against program or erase opera-
tions. When Write Protect, WP, is at V
two (in the bottom configuration) or last two (in the
14/63
IL
, the internal address counter advances. If
IH
, indicates that new data is or will be
powered from V
DDQ
IH
, the internal
, designers
IH
IL
.
IL
the first
, or on
IL
, the
IL
.
top configuration) parameter blocks and all main
blocks are locked. When Write Protect WP is at
V
no other protection is used.
Supply Voltage (V
is the core power supply. All internal circuits draw
their current from the V
gram/Erase Controller.
Output Supply Voltage (V
ply Voltage, V
for all operations (Read, Program and Erase) used
for DQ0-DQ31 when used as outputs.
Input Supply Voltage (V
ply Voltage, V
signal. Input signals are: K, B, L, W, GD, G, E, A0-
A18 and D0-D31, when used as inputs.
Program/Erase Supply Voltage (V
gram/Erase Supply Voltage, V
gram and erase operations. The memory normally
executes program and erase operations at V
voltage levels. In a manufacturing environment,
programming may be speeded up by applying a
higher voltage level, V
The voltage level V
of 80 hours over a maximum of 1000 cycles.
Stressing the device beyond these limits could
damage the device.
Ground (V
reference for the internal supply voltage V
Ground V
input supplies V
connect V
Note: A 0.1 F capacitor should be connected
between the Supply Voltages, V
V
ple the current surges from the power supply.
The PCB track widths must be sufficient to car-
ry the currents required during all operations
of the parts, see Table 15, DC Characteristics,
for maximum current supply requirements.
Don’t Use (DU). This pin should not be used as it
is internally connected. Its voltage level can be be-
tween V
Not Connected (NC). This pin is not physically
connected to the device.
IH
DDIN
all the blocks can be programmed or erased, if
and the Grounds, V
SS
SSQ
SS
SS
and V
and V
DDQ
DDIN
and V
is the reference for the output and
DDQ,
DDQ
, is the output buffer power supply
, is the power supply for all input
SSQ
DD
PPH
SSQ
and V
or leave it unconnected.
). The Supply Voltage, V
PPH
together.
DD
may be applied for a total
). The Ground V
DDQIN
, to the V
SS
DDQIN
pin, including the Pro-
DDQ
and V
PP
). The Output Sup-
). The Input Sup-
. It is essential to
, is used for pro-
PP
DD
SSQ
PP
, V
pin.
). The Pro-
to decou-
SS
DDQ
DD
is the
. The
and
PP1
DD
,