M58BW016DB70T3FF

Manufacturer Part NumberM58BW016DB70T3FF
Description16 Mbit (512 Kb x 32, boot block, burst) 3 V supply Flash memories
ManufacturerSTMICROELECTRONICS [STMicroelectronics]
M58BW016DB70T3FF datasheet
 
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Features
Supply voltage
– V
= 2.7 V to 3.6 V for Program, Erase
DD
and Read
– V
= V
= 2.4 V to 3.6 V for I/O
DDQ
DDQIN
buffers
– V
= 12 V for Fast Program (optional)
PP
High performance
– Access times: 70, 80 ns
– 56 MHz effective zero wait-state Burst
Read
– Synchronous Burst Read
– Asynchronous Page Read
Hardware block protection
– WP pin for Write Protect of the 4 outermost
parameter blocks and all main blocks
– RP pin for Write Protect of all blocks
Optimized for FDI drivers
– Fast Program / Erase Suspend latency
time < 6 µs
– Common Flash interface
Memory blocks
– 8 parameters blocks (top or bottom)
– 31 main blocks
Low power consumption
– 5 µA typical Deep Power-down
– 60 µA typical standby for M58BW016DT/B
150 µA typical standby for M58BW016FT/B
– Automatic standby after Asynchronous
Read
Electronic signature
– Manufacturer code: 20h
– Top device code: 8836h
– Bottom device code: 8835h
®
ECOPACK
packages available
October 2007
M58BW016DB M58BW016DT
M58BW016FT M58BW016FB
16 Mbit (512 Kb x 32, boot block, burst)
3 V supply Flash memories
LBGA80 10 × 12 mm
Rev 14
PQFP80 (T)
BGA
1/69
www.st.com
1

M58BW016DB70T3FF Summary of contents

  • Page 1

    ... RP pin for Write Protect of all blocks Optimized for FDI drivers – Fast Program / Erase Suspend latency time < 6 µs – Common Flash interface Memory blocks – 8 parameters blocks (top or bottom) – 31 main blocks Low power consumption – 5 µA typical Deep Power-down – ...

  • Page 2

    Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 3

    ... Synchronous Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.1 3.2.2 3.3 Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3 Read Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.5 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.6 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.7 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.8 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.10 Set Burst Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . 32 5 Status Register ...

  • Page 4

    Contents 5.6 Program Suspend Status (bit ...

  • Page 5

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 6

    List of figures List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 7

    ... Status and the Burst Configuration Registers are cleared. A recovery time is required when the RP input goes High. The memory is offered in a PQFP80 ( mm) and LBGA80 (10 × 12 mm) package. In order to meet environmental requirements, ST offers the devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97 ...

  • Page 8

    Description In the present document, M58BW016DT, M58BW016DB, M58BW016FT and M58BW016FB will be referred to as M58BW016 unless otherwise specified. Figure 1. Logic diagram 8/69 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB DDQ V DDQIN V PP A0-A18 ...

  • Page 9

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 1. Signal names Signal A0-A18 DQ0-DQ7 DQ8-DQ15 DQ16-DQ31 DDQ V DDQIN SSQ NC DU Description Address inputs ...

  • Page 10

    Description Figure 2. PQFP connections (top view through package) DQ16 DQ17 DQ18 DQ19 V DDQ V SSQ DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 V DDQ V SSQ DQ28 DQ29 DQ30 DQ31 10/69 M58BW016DT, M58BW016DB, ...

  • Page 11

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 3. LBGA connections (top view through package A15 B A16 C A17 D DQ3 E V DDQ F V SSQ G V DDQ H DQ13 I DQ15 J V DDQIN 1.1 Block protection ...

  • Page 12

    Description Table 2. M58BW016DT and M58BW016FT top boot block addresses # ...

  • Page 13

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 3. M58BW016DB and M58BW016FB bottom boot block addresses # ...

  • Page 14

    ... Address inputs (A0-A18) The address inputs are used to select the cells to access in the memory array during Bus operations either to read or to program data. During Bus Write operations they control the commands sent to the command interface of the Program/Erase controller. Chip Enable must be Low when selecting the addresses ...

  • Page 15

    ... Read operations. In Synchronous Burst Read operations the address is latched on the active edge of the Clock when Latch Enable is Low, V change without affecting the address used by the memory. When Latch Enable is Low, V the latch is transparent. Latch Enable, L, can remain at V and Write operations. ...

  • Page 16

    ... Valid Data Ready (R) The Valid Data Ready output open drain output that can be used, during Synchronous Burst Read operations, to identify if the memory is ready to output data or not. The Valid Data Ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before ...

  • Page 17

    ... The input supply voltage GD A0-A18 and DQ0-DQ31, when used as inputs. 2.16 Program/Erase supply voltage (V The Program/Erase supply voltage, V memory normally executes program and erase operations at V manufacturing environment, programming may be speeded up by applying a higher voltage level the V PPH The voltage level V cycles ...

  • Page 18

    ... Asynchronous Latch Controlled Bus Read Asynchronous Latch Controlled Bus Read operations read from the memory cells or specific registers in the command interface. The address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses ...

  • Page 19

    ... Asynchronous Latch Controlled Bus Write Asynchronous Latch Controlled Bus Write operations write to the command interface to send commands to the memory or to latch addresses and input data to program. Bus Write operations are asynchronous, the clock Don’t care during Bus Write operations. ...

  • Page 20

    ... Two codes identifying the manufacturer and the device can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of the memory. The electronic signature is output by giving the Read Electronic Signature command. The manufacturer code is output when all the address inputs are at V ...

  • Page 21

    ... After an initial memory latency time, the memory outputs data each clock cycle (or two clock cycles depending on the value of M9). The Burst Address Advance B input controls the memory burst output. The second burst output is on the next clock valid edge after the Burst Address Advance B has been pulled Low. ...

  • Page 22

    Bus operations Valid Data Ready may be configured (by bit M8 of Burst Configuration Register valid immediately at the valid clock edge or one data cycle before the valid clock edge. Synchronous Burst Read will be suspended if ...

  • Page 23

    ... The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is ’0’ the memory outputs from interleaved addresses; when the Burst Type bit is ’1’ the memory outputs from sequential addresses. See Burst type definition, for the sequence of addresses output from a given starting address in each mode ...

  • Page 24

    ... Table 7: Burst Configuration Register that the memory accepts; output from a given starting address for each length. If either a Continuous Wrap Burst Read has been initiated the device will output data synchronously ...

  • Page 25

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 7. Burst Configuration Register Bit M15 M14 M13-M11 M10 M9 M8 Valid Data Ready M7 M6 Valid Clock Edge M5-M4 M3 M2- latencies can be calculated as: (t number from ...

  • Page 26

    Bus operations Table 8. Burst type definition Starting address sequential interleaved 0 0 0-1-2-3 0-1-2 1-2-3-0 1-0-3 2-3-0-1 2-3-0 3-0-1-2 3-2-1 – – 0 ...

  • Page 27

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 4. Example Burst Configuration X-1-1 ADD VALID L DQ 4-1-1-1 DQ 5-1-1-1 DQ 6-1-1-1 DQ 7-1-1-1 DQ 8-1-1-1 Figure 5. Example Burst Configuration X-2-2 ADD VALID L DQ 5-2-2-2 ...

  • Page 28

    ... Read Memory Array command The Read Memory Array command returns the memory to Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent read operations will output the addressed memory array data. Once the command is issued the memory remains in Read mode until another command is issued ...

  • Page 29

    ... The Clear Status Register command can be used to reset bits and 5 in the Status Register to ‘0’. One Bus Write is required to issue the Clear Status Register command. Once the command is issued the memory returns to its previous mode, subsequent Bus Read operations continue to output the same data. ...

  • Page 30

    ... Block Erase command. 4.7 Program command The Program command is used to program the memory array. Two Bus Write operations are required to issue the command; the first write cycle sets up the Program command, the second write cycle latches the address and data to be programmed in the Program/Erase controller and starts it ...

  • Page 31

    ... Program/Erase Controller Status bit (bit 7) to find out when the Program/Erase controller has paused; no other commands will be accepted until the Program/Erase controller has paused. After the Program/Erase controller has paused, the memory will continue to output the Status Register until another command is issued. ...

  • Page 32

    ... The first cycle writes the setup command and the address corresponding to the Set Burst Configuration Register content. The second cycle writes the Burst Configuration Register data and the confirm command. Once the command is issued the memory returns to Read mode Read Memory Array command had been issued. ...

  • Page 33

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 10. Program, erase times and program, erase endurance cycles Parameters Parameter Block (64 Kb) Program Main Block (512 Kb) Program Parameter Block Erase Main Block Erase Program Suspend Latency time Erase Suspend Latency time Program/Erase ...

  • Page 34

    ... When the Erase Suspend Status bit is set to ‘0’, the Program/Erase controller is active or has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns to ‘ ...

  • Page 35

    ... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 5.3 Erase Status (bit 5) The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase controller inactive). ...

  • Page 36

    ... When the Program Suspend Status bit is set to ‘0’, the Program/Erase controller is active or has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Program Suspend Status bit returns to ‘ ...

  • Page 37

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 6 Maximum ratings Stressing the device above the ratings listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated ...

  • Page 38

    DC and AC parameters 7 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from ...

  • Page 39

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 7. AC measurement load circuit Table 14. Device capacitance Symbol C Input capacitance IN C Output capacitance OUT ° MHz A 2. Sampled only, not 100% tested. 1.3 ...

  • Page 40

    DC and AC parameters Table 15. DC characteristics Symbol Parameter I Input Leakage current LI I Output Leakage current LO I Supply current (Random Read) DD (1) I Supply current (Power-up) DDP-UP I Supply current (Burst Read) DDB Supply current ...

  • Page 41

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 8. Asynchronous Bus Read AC waveforms A0-A18 DQ0-DQ31 . Table 16. Asynchronous Bus Read AC characteristics Symbol t Address Valid to Address Valid AVAV t Address Valid to Output Valid AVQV ...

  • Page 42

    DC and AC parameters Figure 9. Asynchronous Latch Controlled Bus Read AC waveforms A0-A18 tAVLL L tLHLL E G DQ0-DQ31 Table 17. Asynchronous Latch Controlled Bus Read AC characteristics Symbol t Address Valid to Latch Enable Low AVLL t Chip ...

  • Page 43

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 10. Asynchronous Page Read AC waveforms A0-A1 DQ0-DQ31 Table 18. Asynchronous Page Read AC characteristics Symbol t Address Valid to Output Valid AVQV1 t Address Transition to Output Transition AXQX 1. For other timings see ...

  • Page 44

    DC and AC parameters Figure 11. Asynchronous Write AC waveforms 44/69 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB ...

  • Page 45

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 12. Asynchronous Latch Controlled Write AC waveforms DC and AC parameters 45/69 ...

  • Page 46

    DC and AC parameters Table 19. Asynchronous Write and Latch Controlled Write AC characteristics Symbol t Address Valid to Latch Enable Low AVLL t Address Valid to Write Enable High AVWH t Data Input Valid to Write Enable High DVWH ...

  • Page 47

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 13. Synchronous Burst Read (data valid from ‘n’ clock rising edge) DC and AC parameters 47/69 ...

  • Page 48

    DC and AC parameters Table 20. Synchronous Burst Read AC characteristics Symbol t Address Valid to Latch Enable Low AVLL Burst Address Advance High to Valid t BHKH Clock Edge Burst Address Advance Low to Valid t BLKH Clock Edge ...

  • Page 49

    ... open drain output with an internal pull up resistor Ω. typically 300 k for a single memory on the R bus, should be used to give the data valid set up time required to recognize that valid data is available on the next valid clock edge. Figure 16. Synchronous Burst Read - Burst Address Advance ...

  • Page 50

    DC and AC parameters Figure 17. Reset, Power-down and Power-up AC waveforms - control pins low tVDHPH VDD, VDDQ Figure 18. Reset, Power-down and Power-up AC waveforms - control pins toggling ...

  • Page 51

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 21. Reset, Power-down and Power-up AC characteristics Symbol t Reset/Power-down High to Chip Enable Low PHEL t Reset/Power-down High to Latch Enable Low PHLL (1) t Reset/Power-down High to Output Valid PHQV t Reset/Power-down High ...

  • Page 52

    Package mechanical 8 Package mechanical Figure 19. PQFP80 - 80 lead plastic quad flat pack, package outline Nd QFP-B 1. Drawing is not to scale. Table 22. PQFP80 - 80 lead plastic quad flat pack, package mechanical data Symbol A ...

  • Page 53

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 20. LBGA80 10 × × 10 active ball array pitch, package outline Drawing is not to scale. Table 23. LBGA80 10 × ...

  • Page 54

    ... AEC Q001 & Q002 or equivalent. Note: Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. ...

  • Page 55

    ... Common Flash interface (CFI) The common Flash interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary ...

  • Page 56

    ... Available Data n 15h 2 number of bytes memory size 03h Device interface sync./async. 00h Organization sync./async. 00h n Page size in bytes, 2 00h 02h Bit7-0 = number of Erase Block regions in device 1Eh Number (n-1) of blocks of identical size ...

  • Page 57

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 29. Extended query information Address Address offset A18-A0 (P)h 35h (P+1)h 36h (P+2)h 37h (P+3)h 38h (P+4)h 39h (P+5)h 3Ah (P+6)h 3Bh (P+7)h 3Ch (P+8)h 3Dh (P+9)h 3Eh (P+A)h 3Fh Data (Hex) 50h "P" 52h ...

  • Page 58

    ... Error (1) NO Program to Protect Block Error Program Command: – write 40h – write Address & Data (memory enters read status state after the Program command) do: – read status register ( must be toggled) while invalid error: – error handler Program error: – ...

  • Page 59

    ... Program/Erase Suspend Command: – write B0h – write 70h do: – read status register while Program completed Read Memory Array Command: – write FFh – one or more data reads from other blocks Program Erase Resume Command: – write D0h to resume erasure – ...

  • Page 60

    ... Error (1) NO Erase to Protected Block Error Erase Command: – write 20h – write Block Address (A11-A18) & D0h (memory enters read status state after the Erase command) do: – read status register ( must be toggled) if Erase command given execute suspend erase loop while invalid error: – ...

  • Page 61

    ... Program/Erase Suspend Command: – write B0h – write 70h do: – read status register while Erase completed Read Memory Array command: – write FFh – one or more data reads from other blocks Program/Erase Resume command: – write D0h to resume the Erase operation – ...

  • Page 62

    Flowcharts Figure 25. Power-up sequence followed by Synchronous Burst Read Power-up or Reset Asynchronous Read Write 60h command Write 03h with A15-A0 BCR inputs Synchronous Read 62/69 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB BCR bit 15 = '1' Set Burst Configuration Register ...

  • Page 63

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 26. Command interface and Program/Erase controller flowchart (a) WAIT FOR COMMAND WRITE NO 90h YES READ ELEC. 98h SIGNATURE READ CFI ERASE COMMAND ERROR READ STATUS B NO YES NO 70h YES READ NO 20h ...

  • Page 64

    Flowcharts Figure 27. Command interface and Program/Erase controller flowchart (b) E 64/69 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB NO 60h YES NO FFh SET BCR SET_UP YES NO 03h YES D AI03836b ...

  • Page 65

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 28. Command interface and Program/Erase controller flowchart ( READ STATUS READ ARRAY YES ERASE SUSPENDED YES YES 70h NO YES PROGRAM 40h SET_UP NO NO YES READ D0h STATUS Flowcharts A ERASE YES ...

  • Page 66

    Flowcharts Figure 29. Command interface and Program/Erase controller flowchart ( READ STATUS READ ARRAY 66/69 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB YES YES PROGRAM SUSPENDED YES YES 70h NO NO YES READ D0h STATUS C PROGRAM READY NO NO READ ...

  • Page 67

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Revision history Table 30. Document revision history Date Version January-2001 05-Jun-2001 15-Jun-2001 17-Jul-2001 17-Dec-2001 17-Jan-2002 30-Aug-2002 4-Sep-2002 13-May-2003 16-Oct-2003 03-Mar-2005 06-Sep-2005 3-Mar-2006 16-Jun-2006 01 First Issue. 02 Major rewrite and restructure and Ne values ...

  • Page 68

    Revision history Table 30. Document revision history (continued) Date Version 09-Nov-2006 24-Nov-2006 05-Oct-2007 68/69 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB LBGA80 package added (see M58BW016FT and M58BW016FB behavior in Burst mode specified under Section 3.2.1: Synchronous Burst and I ...

  • Page 69

    M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services ...