M58BW016DB70T3FF STMICROELECTRONICS [STMicroelectronics], M58BW016DB70T3FF Datasheet - Page 22

• Manufacturer Part Number: M58BW016DB70T3FF
• Description: 16 Mbit (512 Kb x 32, boot block, burst) 3 V supply Flash memories
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Bus operations
3.2.2
22/69
Valid Data Ready may be configured (by bit M8 of Burst Configuration Register) to be valid
immediately at the valid clock edge or one data cycle before the valid clock edge.
Synchronous Burst Read will be suspended if Burst Address Advance, B, goes High, V
If Output Enable is at V
If Output Enable, G, is at V
Advance, B, is at V
K valid edge.
The Synchronous Burst Read timing diagrams and AC characteristics are described in the
AC and DC parameters section. See
Table
Synchronous Burst Read Suspend
During a Synchronous Burst Read operation it is possible to suspend the operation, freeing
the data bus for other higher priority devices.
A valid Synchronous Burst Read operation is suspended when both Output Enable and
Burst Address Advance are High, V
the Burst counter and the Output Enable going High, V
Synchronous Burst Read operation can be resumed by setting Output Enable Low.
Table 6.
1. X = Don't care, V
2. M15 = 0, bit M15 is in the Burst Configuration Register.
3. T = transition, see M6 in the Burst Configuration Register for details on the active edge of K.
Synchronous
Burst Read
Bus operation
20.
Synchronous Burst Read Bus operations
IL
Address Latch
Read
Read Suspend
Read Resume
Burst Address
Advance
Read Abort, E
Read Abort, RP
or V
IL
the internal Burst Address counter is incremented at each Burst Clock
IH
IL
.
and Output Disable is at V
Step
IH
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
or Output Disable, GD, is at V
IH
Figure
. The Burst Address Advance going High, V
V
V
V
V
V
V
E
X
IH
IL
IL
IL
IL
IL
13,
V
V
V
V
V
G
X
X
IH
IH
IH
IL
IL
Figure
GD RP K
V
V
X
X
X
X
X
IH
IH
IH
, the last data is still valid.
IH
14,
V
V
V
V
V
V
V
, inhibits the data outputs. The
IH
IH
IH
IH
IH
IH
IL
(1)(2)
Figure 15
IL
, but the Burst Address
T
T
X
T
T
X
X
(3)
V
V
V
V
V
X
X
L
IH
IH
IH
IH
IL
and
V
V
V
V
B
X
X
X
IH
IL
IL
IL
Figure
Address input
Data output
Data output
DQ0-DQ31
A0-A18
High-Z
High-Z
High-Z
High-Z
16, and
IH
, stops
IH
.