M58BW032BB45T3T

Manufacturer Part NumberM58BW032BB45T3T
Description32 Mbit (1Mb x32, Boot Block, Burst) 3.3V Supply Flash Memory
ManufacturerSTMICROELECTRONICS [STMicroelectronics]
M58BW032BB45T3T datasheet
 
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FEATURES SUMMARY
SUPPLY VOLTAGE
V
= 3.0V to 3.6V for Program, Erase
DD
and Read
V
= V
= 1.6V to 3.6V for I/O
DDQ
DDQIN
Buffers
HIGH PERFORMANCE
Access Time: 45, 55 and 60ns
75MHz Effective Zero Wait-State Burst
Read
Synchronous Burst Reads
Asynchronous Page Reads
MEMORY ORGANIZATION
– Eight 64 Kbit small parameter Blocks
– Four 128Kbit large parameter Blocks (of
which one is OTP)
– Sixty-two 512Kbit main Blocks
HARDWARE BLOCK PROTECTION
WP pin Lock Program and Erase
V
signal for Program/Erase Enable
PEN
SOFTWARE BLOCK PROTECTION
Tuning Protection to Lock Program and
Erase with 64-bit User Programmable
Password (M58BW032B version only)
SECURITY
64-bit Unique Device Identifier (UID)
FAST PROGRAMMING
Write to Buffer and Program capability
OPTIMIZED FOR FDI DRIVERS
Common Flash Interface (CFI)
Fast Program/Erase Suspend feature in
each block
LOW POWER CONSUMPTION
100µA Typical Standby
November 2004
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M58BW032BT, M58BW032BB
M58BW032DT, M58BW032DB
32 Mbit (1Mb x32, Boot Block, Burst)
3.3V Supply Flash Memory
Figure 1. Packages
ELECTRONIC SIGNATURE
Manufacturer Code: 20h
Top Device Code M58BW032xT: 8838h
Bottom Device Code M58BW032xB:
8837h
OPERATING TEMPERATURE RANGE
Automotive (Grade 3):
Industrial (Grade 6):
PRELIMINARY DATA
PQFP80 (T)
BGA
LBGA80 (ZA)
10 x 8 ball array
40 to 125°C
40 to 90°C
1/60

M58BW032BB45T3T Summary of contents

  • Page 1

    ... Typical Standby November 2004 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. M58BW032BT, M58BW032BB M58BW032DT, M58BW032DB 32 Mbit (1Mb x32, Boot Block, Burst) 3.3V Supply Flash Memory Figure 1. Packages ELECTRONIC SIGNATURE – Manufacturer Code: 20h – ...

  • Page 2

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 3

    ... Wrap Burst Bit (M3 Burst Length Bit (M2-M0 Table 6. Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 5. Example Burst Configuration X-1-1 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Erase All Main Blocks Command ...

  • Page 4

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Block Protection Status (Bit ...

  • Page 5

    Figure 25.Unlock Device and Program a Tuning Protected Block Flowchart . . . . . . . . . . . . . . . . . 51 Figure 26.Unlock Device and Erase a Tuning Protected Block Flowchart . . ...

  • Page 6

    ... Status and Burst Con- figuration Registers are cleared. A recovery time is required when the RP input goes High. A manufacturer and device code are available. They can be read from the memory allowing pro- gramming equipment or applications to automati- cally match their interface to the characteristics of the memory. ...

  • Page 7

    Figure 2. Logic Diagram DDQ V DDQIN A0-A19 K L M58BW032BT E M58BW032BB RP M58BW032DT M58BW032DB SSQ M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Table 1. Signal Names A0-A19 DQ0-DQ7 V PEN ...

  • Page 8

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 3. LBGA Connections (Top view through package A15 A14 B A16 A13 C A17 A18 D DQ3 DQ0 E V DDQ DQ4 F V SSQ DQ7 G V DDQ DQ8 H DQ13 DQ12 ...

  • Page 9

    Figure 4. PQFP Connections (Top view through package) DQ16 1 DQ17 DQ18 DQ19 V DDQ V SSQ DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 12 DQ26 DQ27 V DDQ V SSQ DQ28 DQ29 DQ30 DQ31 M58BW032BT, ...

  • Page 10

    ... M58BW032B version. The code is written once in the Tuning Protection Register and cannot be erased. When shipped the flash memory will have the Tuning Protection Code bits set to ‘1'. The user can program a ‘0’ in any of the 64 positions. Once programmed it is not possible to reset a bit to ‘ ...

  • Page 11

    Table 2. Top Boot Block Addresses, M58BW032BT, M58BW032DT # Size (Kbit) Address Range 73 128 FF000h-FFFFh 72 128 FE000h-FEFFFh 71 128 FD000h-FDFFFh 70 128 FC000h-FCFFFh 69 64 FB800h-FBFFFh 68 64 FB000h-FB7FFh 67 64 FA800h-FAFFFh 66 64 FA000h-FA7FFh 65 64 F9800h-F9FFFh ...

  • Page 12

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Table 3. Bottom Boot Block Addresses, M58BW032BB, M58BW032DB # Size (Kbit) Address Range 73 512 FC000h-FFFFFh 72 512 F8000h-FBFFFh 71 512 F4000h-F7FFFh 70 512 F0000h-F3FFFh 69 512 EC000h-EFFFFh 68 512 E8000h-EBFFFh 67 512 E4000h-E7FFFh 66 512 ...

  • Page 13

    ... IL (I DD1 data outputs are high impedance. After Reset/Power-Down goes High, V memory will be ready for Bus Read operations af- ter a delay PHWL If Reset/Power-Down goes Low, V Block Erase, a Program or a Tuning Protection Program the operation is aborted time of t ...

  • Page 14

    ... The Burst Address Advance, B, may be tied to V Valid Data Ready (R). The Valid Data Ready output, R, can be used during Synchronous Burst Read operations to identify if the memory is ready to output data or not. The Valid Data Ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before ...

  • Page 15

    ... Figure 10., Asynchronous Page Read AC Waveforms, and Read AC outputs become valid. Asynchronous Bus Write. Asynchronous Write operations write to the Command Interface in order to send commands to the memory or to latch addresses and input data to program. Bus and Table Write operations are asynchronous, the clock, K, Characteristics., is don’ ...

  • Page 16

    ... Asynchronous Latch Controlled Bus Write. Asynchronous Latch Controlled Bus Write opera- tions write to the Command Interface in order to send commands to the memory or to latch ad- dresses and input data to program. Bus Write op- erations are asynchronous, the clock don’t care during Bus Write operations. ...

  • Page 17

    ... R= Rising Edge. M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB 5 When Valid Data Ready is Low on the rising clock edge, no new data is available and the memory does not increment the internal address counter at the active clock edge even if Burst Address Ad- vance Low. Valid Data Ready may be configured (by bit M8 of ...

  • Page 18

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Burst Configuration Register The Burst Configuration Register is used to config- ure the type of bus access that the memory will perform. The Burst Configuration Register is set through the Command Interface and will retain its informa- tion until it is re-configured, the device is reset, or the device goes into Reset/Power-Down mode ...

  • Page 19

    Table 6. Burst Configuration Register Bit Description M15 Read Select M14 Standby Disable (1) M13-M11 X-Latency M10 Reserved (2) M9 Y-Latency M8 Valid Data Ready M7-M4 Reserved M3 Wrapping M2-M0 Burst Length Note latencies can be calculated as: ...

  • Page 20

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Table 7. Burst Type Definition Starting M 3 Address Sequential 0 0 0-1-2 1-2-3 2-3-0 3-0-1 0-1-2-3 1 ...

  • Page 21

    Figure 5. Example Burst Configuration X-1-1 ADD VALID L DQ 3-1-1-1 DQ 4-1-1-1 DQ 5-1-1-1 DQ 6-1-1-1 DQ 7-1-1-1 DQ 8-1-1-1 M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB VALID VALID VALID VALID VALID VALID 6 7 ...

  • Page 22

    ... Read Memory Array Command The Read Memory Array command returns the memory to Read mode. One Bus Write cycle is re- quired to issue the Read Memory Array command and return the memory to Read mode. Subse- quent read operations will output the addressed memory array data ...

  • Page 23

    ... A protected block must be unprotected using the Blocks Unprotect command. During a Write to Buffer and Program operation Commands, for the memory will only accept the Read Status Reg- ister and the Program/Erase Suspend commands. All other commands are ignored. The Write to Buffer and Program command can be executed using V performed ...

  • Page 24

    ... Status Register with bits 4 and 5 set to ‘1’. Once the command is issued the memory re- turns to Read mode Read Memory Array command had been issued. The value for the Burst Configuration Register is always presented on A0-A15 A0 A1, etc. ...

  • Page 25

    ... Status Register bit0 ‘0’ the device is locked ‘1’ the device is un- locked. If the device is still locked a Read Memory Array command must be issued before re-issuing the Tuning Protection Unlock command. ...

  • Page 26

    ... The first cycle writes the setup command The second write cycle specifies the address of the block to unprotect and confirms the command. If the command is not confirmed, Table 8. Commands Command Read Memory Array (2) Read Electronic Signature Read Status Register Read Query Clear Status Register ...

  • Page 27

    Table 9. Read Electronic Signature Code Manufacturer M58BW032xT Device M58BW032xB Burst Configuration Register Block Protection Configuration Register Note version of the device. 2. BCR= Burst Configuration Register. 3. SBA is the start address of each ...

  • Page 28

    ... The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Erase Status bit is set to ‘0’, the memory has successfully verified that the block has erased correctly. When the Erase Status bit is set to ‘1’, ...

  • Page 29

    ... Program/Erase Controller is active or has com- pleted its operation; when the bit is set to ‘1’, a Pro- gram/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is is- sued the Program Suspend Status bit returns to ‘ ...

  • Page 30

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB MAXIMUM RATING Stressing the device above the ratings listed in ble 12., Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any ...

  • Page 31

    DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC characteristics Tables that follow, are de- rived from tests performed ...

  • Page 32

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Table 15. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO (1) Supply Current (Random Read (1) Supply Current (Burst Read) I DDB (1) Supply Current (Standby) I DD1 ...

  • Page 33

    Figure 8. Asynchronous Bus Read AC Waveforms A0-A19 DQ0-DQ31 Table 16. Asynchronous Bus Read AC Characteristics. Symbol Parameter t Address Valid to Address Valid AVAV t Address Valid to Output Valid AVQV t Address Transition to ...

  • Page 34

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 9. Asynchronous Latch Controlled Bus Read AC Waveforms A0-A19 tAVLL L tLHLL E G DQ0-DQ31 Table 17. Asynchronous Latch Controlled Bus Read AC Characteristics Symbol Parameter t Address Valid to Latch Enable Low AVLL t ...

  • Page 35

    Figure 10. Asynchronous Page Read AC Waveforms A0-A1 DQ0-DQ31 Table 18. Asynchronous Page Read AC Characteristics Symbol Parameter t Address Valid to Output Valid AVQV1 t Address Transition to Output Transition AXQX Note: For other timings see Table 16., Asynchronous ...

  • Page 36

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 11. Asynchronous Write AC Waveform 36/60 ...

  • Page 37

    Figure 12. Asynchronous Latch Controlled Write AC Waveform M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB 37/60 ...

  • Page 38

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics Symbol Parameter t Address Valid to Latch Enable Low AVLL t Address Valid to Write Enable High AVWH t Data Input Valid to Write Enable High ...

  • Page 39

    Figure 13. Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge) M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB 39/60 ...

  • Page 40

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Table 20. Synchronous Burst Read AC Characteristics Symbol Parameter t Address Valid to Latch Enable Low AVLL Burst Address Advance High to Valid Clock t BHKH Edge Burst Address Advance Low to Valid Clock t BLKH ...

  • Page 41

    Figure 15. Synchronous Burst Read - Continuous - Valid Data Ready Output K (1) Output Note: Valid Data Ready = Valid Low during valid clock edge 1. V= Valid output. 2. The internal timing of R follows ...

  • Page 42

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 17. Reset, Power-Down and Power-up AC Waveform tVDHPH VDD, VDDQ Table 21. Reset, Power-Down and Power-up AC Characteristics Symbol t Reset/Power-down High to Chip Enable Low PHEL (1) Reset/Power-down High ...

  • Page 43

    PACKAGE MECHANICAL Figure 18. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Bottom View Package Outline BALL "A1" Note: Drawing is not to scale. Table 22. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Package Mechanical ...

  • Page 44

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 19. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline QFP-B Note: Drawing is not to scale. Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data Symbol ...

  • Page 45

    ... Option T = Tape & Reel Packing Note: Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de- vice, please contact the ST Sales Office nearest to you. ...

  • Page 46

    ... Error (1) NO Program to Protect Block Error Program Command: – write 40h, Address AAh – write Address & Data (memory enters read status state after the Program command) do: – read status register ( must be toggled) while PEN invalid error: – ...

  • Page 47

    ... Program/Erase Suspend Command: – write B0h – write 70h do: – read status register while Program completed Read Memory Array Command: – write FFh – one or more data reads from other blocks Program Erase Resume Command: – write D0h to resume programming – ...

  • Page 48

    ... Erase to Protected Block Error Erase Command: – write 20h, Address 55h – write Block Address (A11-A19) & D0h (memory enters read status state after the Erase command) do: – read status register ( must be toggled) if Erase command given execute suspend erase loop ...

  • Page 49

    ... Program/Erase Suspend Command: – write B0h – write 70h do: – read status register while Erase completed Read Memory Array command: – write FFh – one or more data reads from other blocks Program/Erase Resume command: – write D0h to resume the Erase operation – ...

  • Page 50

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 24. Unlock Device and Change Tuning Protection Code Flowchart Reset Device locked by tuning code Add: don't care Data: 78h Add: 00000h Data: First 32 bit Add: don't care Data: FFh Issue ...

  • Page 51

    Figure 25. Unlock Device and Program a Tuning Protected Block Flowchart Reset Device locked by tuning code Add: don't care Data: 78h Add: 00000h Data: First 32 bit Add: don't care Data: FFh Issue Read command Add: ...

  • Page 52

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 26. Unlock Device and Erase a Tuning Protected Block Flowchart Reset Device locked by tuning code Add: don't care Data: 78h Add: 00000h Data: First 32 bit Add: don't care Data: FFh ...

  • Page 53

    Figure 27. Power-up Sequence to Burst the Flash Power-up or Reset Asynchronous Read Write 60h command Write 03h with A15-A0 BCR inputs Synchronous Read M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB BCR bit 15 = '1' Set Burst Configuration Register Command: – write ...

  • Page 54

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 28. Command Interface and Program Erase Controller Flowchart (a) WAIT FOR COMMAND WRITE NO 90h YES READ ELEC. 98h SIGNATURE READ CFI ERASE COMMAND ERROR READ STATUS B 54/60 NO YES NO 70h YES READ ...

  • Page 55

    Figure 29. Command Interface and Program Erase Controller Flowchart ( 48h YES TP 78h PROGRAM SET_UP F TP UNLOCK SET_UP G M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB NO YES NO 60h YES NO FFh SET BCR SET_UP YES NO 03h ...

  • Page 56

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 30. Command Interface and Program Erase Controller Flowchart (c) B READ STATUS READ ARRAY 56/60 NO ERASE SUSPENDED YES YES 70h NO YES PROGRAM 40h SET_UP NO NO YES READ D0h STATUS A ERASE YES ...

  • Page 57

    Figure 31. Command Interface and Program Erase Controller Flowchart ( READ STATUS READ ARRAY M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB YES YES PROGRAM SUSPENDED YES YES 70h NO NO YES READ D0h STATUS C PROGRAM READY NO NO READ B0h ...

  • Page 58

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 32. Command Interface and Program Erase Controller Flowchart (e) 58/ PROGRAM YES NO READ READY STATUS UNLOCK YES NO READ READY STATUS AI03839 ...

  • Page 59

    REVISION HISTORY Table 25. Document Revision History Date Version 20-Oct-2003 1.0 21-Oct-2003 1.1 20-Nov-2003 1.2 27-Apr-2004 2.0 30-July-2004 3.0 05-Nov-2004 4.0 M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Revision Details First Issue. Figure 7, AC Measurement Load Circuit modified. I Table 5, DC ...

  • Page 60

    M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may ...