M58BW032BB45T3T STMICROELECTRONICS [STMicroelectronics], M58BW032BB45T3T Datasheet - Page 15

• Manufacturer Part Number: M58BW032BB45T3T
• Description: 32 Mbit (1Mb x32, Boot Block, Burst) 3.3V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

BUS OPERATIONS
Each bus operations that controls the memory is
described in this section, see Tables
Operations, for a summary. The bus operation is
selected through the Burst Configuration Register;
the bits in this register are described at the end of
this section.
On Power-up or after a Hardware Reset the mem-
ory defaults to Asynchronous Bus Read and Asyn-
chronous Bus Write. No synchronous operation
can be performed until the Burst Control Register
has been configured.
The Electronic Signature, Block Protection Config-
uration, CFI or Status Register will be read in
asynchronous mode regardless of the Burst Con-
trol Register settings.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Asynchronous Bus Operations
For asynchronous bus operations refer to Table
together with the following text.
Asynchronous Bus Read. Asynchronous
Read operations read from the memory cells, or
specific registers (Electronic Signature, Block Pro-
tection Configuration Register, Status Register,
CFI and Burst Configuration Register) in the Com-
mand Interface. A valid bus operation involves set-
ting the desired address on the Address Inputs,
applying a Low signal, V
Output Enable and keeping Write Enable and Out-
put Disable High, V
will output the value, see
Bus
16., Asynchronous Bus Read AC
for details of when the output becomes valid.
Asynchronous Read is the default read mode
which the device enters on power-up or on return
from Reset/Power-Down.
Asynchronous Latch Controlled Bus Read.
Asynchronous Latch Controlled Bus Read opera-
tions read from the memory cells or specific regis-
ters in the Command Interface. The address is
latched in the memory before the value is output
on the data bus, allowing the address to change
during the cycle without affecting the address that
the memory uses.
A valid bus operation involves setting the desired
address on the Address Inputs, setting Chip En-
able and Latch Enable Low, V
Enable High, V
ing edge of Latch Enable. Once latched, the Ad-
dress Inputs can change. Set Output Enable Low,
V
IL
, to read the data on the Data Inputs/Outputs;
Read
IH
AC
; the address is latched on the ris-
IH
Waveforms,
. The Data Inputs/Outputs
Figure 8., Asynchronous
IL
, to Chip Enable and
IL
and keeping Write
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Characteristics.,
and
4
and
5
Table
Bus
Bus
4
see Figure
trolled Bus Read AC Waveforms
17., Asynchronous Latch Controlled Bus Read AC
Characteristics, for details on when the output be-
comes valid.
Note that, since the Latch Enable input is transpar-
ent when set Low, V
operations can be performed when the memory is
configured for Asynchronous Latch Enable bus
operations by holding Latch Enable Low, V
throughout the bus operation.
Asynchronous Page Read. Asynchronous
Page Read operations are used to read from sev-
eral addresses within the same memory page.
Each memory page is 4 Double-Words and is ad-
dressed by the address inputs A0 and A1.
Data is read internally and stored in the Page Buff-
er. Valid bus operations are the same as Asyn-
chronous Bus Read operations but with different
timings. The first read operation within the page
has identical timings, subsequent reads within the
same page have much shorter access times. If the
page changes then the normal, longer timings ap-
ply again. Page Read does not support Latched
Controlled Read.
See
Waveforms, and
Read AC
outputs become valid.
Asynchronous Bus Write. Asynchronous
Write operations write to the Command Interface
in order to send commands to the memory or to
latch addresses and input data to program. Bus
Write operations are asynchronous, the clock, K,
is don’t care during Bus Write operations.
A valid Asynchronous Bus Write operation begins
by setting the desired address on the Address In-
puts, and setting Chip Enable, Write Enable and
Latch Enable Low, V
V
puts are latched by the Command Interface on the
rising edge of Chip Enable or Write Enable, which-
ever occurs first. Commands and Input Data are
latched on the rising edge of Chip Enable, E, or
Write Enable, W, whichever occurs first. Output
Enable must remain High, and Output Disable
Low, during the whole Asynchronous Bus Write
operation.
See
form, and
trolled Write AC
timing requirements.
IH
, or Output Disable Low, V
Figure 11., Asynchronous Write AC Wave-
Figure 10., Asynchronous Page Read AC
Characteristics, for details on when the
Asynchronous Write and Latch Con-
Figure 9., Asynchronous Latch Con-
Characteristics, for details of the
Table 18., Asynchronous Page
IL
IL
, Asynchronous Bus Read
, and Output Enable High,
IL
. The Address In-
and
Table
15/60
Bus
IL