M58BW16FB4T3 STMICROELECTRONICS [STMicroelectronics], M58BW16FB4T3 Datasheet
M58BW16FB4T3
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M58BW16FB4T3 Summary of contents
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... M58BW32F memory organization: – Eight 64 Kbit small parameter blocks – Four 128 Kbit large parameter blocks – Sixty-two 512 Kbit main blocks M58BW16F memory organization: – Eight 64 Kbit parameter blocks – Thirty-one 512 Kbit main blocks Hardware block protection – WP pin to protect any block combination from Program and Erase operations – ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Synchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.1 3.2.2 3.3 Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3 Read Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.4 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.5 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.6 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.7 Erase All Main Blocks command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.8 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.9 Write to Buffer and Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 ...
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Contents 5.4.1 5.5 Program Suspend Status (Bit ...
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M58BW16F, M58BW32F List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a Program or Erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards ...
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... Status and Burst Configuration Registers are cleared. A recovery time is required when the RP input goes High. A manufacturer code and a device code are available. They can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of the memory. ...
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M58BW16F, M58BW32F Figure 1. Logic diagram DDQ V DDQIN (1) A0-Amax E K PEN L M58BW32F M58BW16F SSQ Description DQ0-DQ31 R AI13224b 9/81 ...
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Description Table 1. Signal names (1) A0-Amax DQ0-DQ7 DQ8-DQ15 DQ16-DQ31 DDQ V DDQIN PEN SSQ Amax is equal to A18 in ...
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M58BW16F, M58BW32F Figure 2. LBGA connections (top view through package A15 B A16 C A17 D DQ3 E V DDQ F V SSQ G V DDQ H DQ13 J DQ15 K V DDQIN 1. Ball ...
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Description Figure 3. PQFP connections (top view through package) DQ16 DQ17 DQ18 DQ19 V DDQ V SSQ DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 V DDQ V SSQ DQ28 DQ29 DQ30 DQ31 12/81 1 M58BW16F ...
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M58BW16F, M58BW32F 1.1 Block Protection The M58BWxxF features four different levels of block protection. Write Protect Pin, WP, - When WP is Low, V configured in the Block Protection Configuration Register is activated. The Block Protection Configuration Register is volatile. ...
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Description Table 2. M58BW32F top boot block addresses # Size (Kbit ...
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M58BW16F, M58BW32F Table 2. M58BW32F top boot block addresses (continued) # Size (Kbit ...
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Description Table 3. M58BW32F Bottom Boot Block Addresses # ...
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M58BW16F, M58BW32F Table 3. M58BW32F Bottom Boot Block Addresses (continued ...
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Description Table 4. M58BW16F top boot block addresses # 38 37 ( ...
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M58BW16F, M58BW32F Table 5. M58BW16F bottom boot block addresses # ...
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... Address Inputs (A0-Amax) Amax is equal to A18 in the M58BW16F, and to A19 in the M58BW32F. The Address Inputs are used to select the cells to access in the memory array during Bus operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. Chip Enable must be Low when selecting the addresses ...
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... Latch Enable, L). 2.7 Reset/Power-Down (RP) The Reset/Power-Down, RP, is used to apply a hardware reset to the memory. A hardware reset is achieved by holding Reset/Power-Down Low, V inhibited to protect data, the Command Interface and the Program/Erase Controller are reset. The Status Register information is cleared and power consumption is reduced to the ...
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... Valid Data Ready (R) The Valid Data Ready output, R, can be used during Synchronous Burst Read operations to identify if the memory is ready to output data or not. The Valid Data Ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. ...
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M58BW16F, M58BW32F 2.14 Supply Voltage (V The Supply Voltage, V from the V pin, including the Program/Erase Controller. DD 2.15 Output Supply Voltage (V The Output Supply Voltage, V Program and Erase) used for DQ0-DQ31 when used as outputs. 2.16 ...
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... Asynchronous Latch Controlled Bus Read Asynchronous Latch Controlled Bus Read operations read from the memory cells or specific registers in the Command Interface. The address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses ...
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... Asynchronous Latch Controlled Bus Write Asynchronous Latch Controlled Bus Write operations write to the Command Interface in order to send commands to the memory or to latch addresses and input data to program. Bus Write operations are asynchronous, the clock don’t care during Bus Write operations ...
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... Configuration Register to ‘1’ (see 3.1.8 Reset/Power-Down The memory is in Reset/ Power-Down mode when Reset/Power-Down, RP power consumption is reduced to the standby level (I impedance, independent of the Chip Enable, E, Output Enable, G, Output Disable, GD, or Write Enable, W, inputs. In this mode the device is write protected and both the Status and the Burst Configuration Registers are cleared ...
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... Valid Data Ready, R, monitors if the memory burst boundary is exceeded and the Burst Controller of the microprocessor needs to insert wait states. When Valid Data Ready is Low on the rising clock edge, no new data is available and the memory does not increment the internal address counter at the active clock edge even if Burst Address Advance Low. ...
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... Burst Configuration Register The Burst Configuration Register is used to configure the type of bus access that the memory will perform. The Burst Configuration Register is set through the Command Interface and will retain its information until it is re-configured, the device is reset, or the device goes into Reset/Power- Down mode ...
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... Synchronous Burst Read operation. Burst lengths are available. Table 8: Burst Configuration Register that the memory accepts Burst Read operation (no wrap) has been initiated the device will output data synchronously. Depending on the starting address, the device activates the Valid Data Ready output to indicate that a delay is necessary before the data is output ...
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Bus operations Table 8. Burst Configuration Register Bit M15 Read Select M14 Standby Disable M13-M11 X-Latency M10 Reserved M9 Y-Latency M8 Valid Data Ready M7-M4 Reserved M3 Wrapping M2-M0 Burst Length 30/81 Description Value 0 Synchronous Burst Read 1 Asynchronous ...
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M58BW16F, M58BW32F Table 9. Burst type definition Start Address Figure 4. Example burst configuration X-1-1 ADD VALID L DQ 3-1-1-1 DQ 4-1-1-1 DQ 5-1-1-1 DQ 6-1-1-1 DQ 7-1-1-1 ...
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... Read Memory Array command The Read Memory Array command returns the memory to Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent read operations will output the addressed memory array data. Once the command is issued the memory remains in Read mode until another command is issued ...
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... Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Erase operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. ...
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... Program command The Program command is used to program the memory array. Two Bus Write operations are required to issue the command; the first write cycle sets up the Program command, the second write cycle latches the address and data to be programmed and starts the Program/Erase Controller ...
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... Status Register bits 4 and 5 are set to ‘1’ and the operation will abort without affecting the data in the memory array. A protected block must be unprotected using the Blocks Unprotect command. During a Write to Buffer and Program operation the memory will only accept the Read Status Register and the Program/Erase Suspend commands. All other commands are ignored. If PEN operation aborts and the Status Register PEN bit (bit 3) is set to '1' ...
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... Program/Erase Controller Status bit (bit 7) to find out when the Program/Erase Controller has paused; no other commands will be accepted until the Program/Erase Controller has paused. After the Program/Erase Controller has paused, the memory will continue to output the Status Register until another command is issued. ...
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... Burst Configuration Register content written, and confirms the command. If the command is not confirmed, the sequence is aborted and the device outputs the Status Register with bits 4 and 5 set to ‘1’. Once the command is issued the memory returns to Read mode Read Memory Array command had been issued. ...
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... Command interface (1) Table 10. Commands Command Read Memory Array 2 Write (2) Read Electronic Signature 2 Write Read Status Register 1 Read Query 2 Write Clear Status Register 1 Block Erase 2 Erase All Main Blocks 2 any block 2 Program OTP Block 2 Write to Buffer and Program N+4 Write AAh E8h Write ...
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... T = –40 to 125° The minimum effective erase time is defined as the minimum time required between the last Erase Resume command and the next Erase Suspend command for the internal Flash memory Program/Erase Controller to be able to execute its algorithm. Device Amax-A0 ...
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... When the Erase Suspend Status bit is set to ‘0’, the Program/Erase Controller is active or has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns to ‘ ...
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... M58BW16F, M58BW32F 5.3 Erase Status (Bit 5) The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Erase Status bit is set to ‘0’, the memory has successfully verified that the block has erased correctly. When the Erase Status bit is set to ‘ ...
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... When the Program Suspend Status bit is set to ‘0’, the Program/Erase Controller is active or has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Program Suspend Status bit returns to ‘ ...
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M58BW16F, M58BW32F Table 13. Status Register Bits Bit 7 Program/Erase Controller Status 6 Erase Suspend Status 5 Erase Status 4 Program Status, 3 PEN Status bit 2 Program Suspend Status Erase/Program in a Protected 1 Block 0 Reserved Name Logic ...
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Maximum rating 6 Maximum rating Stressing the device above the ratings listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the ...
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M58BW16F, M58BW32F 7 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed ...
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DC and AC parameters Table 16. Device capacitance Symbol C Input Capacitance IN C Output Capacitance OUT 25° MHz A 2. Sampled only, not 100% tested. Table 17. DC characteristics Symbol I Input Leakage ...
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M58BW16F, M58BW32F Figure 7. Asynchronous Bus Read AC waveforms A0-A19 DQ0-DQ31 Figure 8. Asynchronous Latch controlled bus Read AC waveforms A0-A19 L tLHLL E G DQ0-DQ31 tAVAV VALID tAVQV tEHLX tELQX tELQV tGLQX tGLQV OUTPUT See ...
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DC and AC parameters Figure 9. Asynchronous Chip Enable controlled bus Read AC waveforms A0-A19 DQ0-DQ31 Figure 10. Asynchronous Address controlled bus Read AC waveforms A0-A19 DQ0-DQ31 48/81 VALID tLHAX tGLQX tGLQV tELQX tELQV ...
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M58BW16F, M58BW32F Table 18. Asynchronous Bus Read AC characteristics Symbol t Address Valid to Address Valid AVAV t Address Valid to Output Valid AVQV t Address Transition to Output Transition AXQX Chip Enable High to Latch Enable t EHLX Transition ...
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DC and AC parameters Figure 11. Asynchronous Page Read AC waveforms A0-A1 DQ0-DQ31 Table 19. Asynchronous Page Read AC characteristics Symbol Parameter t Address Valid to Output Valid AVQV1 t Address Transition to Output Transition AXQX 1. For other timings ...
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M58BW16F, M58BW32F Figure 12. Asynchronous Write AC waveform DC and AC parameters 51/81 ...
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DC and AC parameters Figure 13. Asynchronous Latch controlled Write AC waveform 52/81 M58BW16F, M58BW32F ...
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M58BW16F, M58BW32F Table 20. Asynchronous Write and Latch controlled Write AC characteristics Symbol Parameter t Address Valid toAddress Valid AVAV t Address Valid to Latch Enable High AVLH t Address Valid to Latch Enable Low AVLL t Address Valid to ...
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DC and AC parameters Figure 14. Synchronous Burst Read, Latch Enable controlled (data valid from ’n’ clock rising edge) 54/81 M58BW16F, M58BW32F ...
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M58BW16F, M58BW32F Figure 15. Synchronous Burst Read, Chip Enable controlled (data valid from ’n’ clock rising edge) DC and AC parameters 55/81 ...
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DC and AC parameters Figure 16. Synchronous Burst Read, Valid Address transition controlled (data valid from ’n’ clock rising edge) 56/81 M58BW16F, M58BW32F ...
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M58BW16F, M58BW32F Figure 17. Synchronous Burst Read (data valid from ’n’ clock rising edge tKHQV DQ0-DQ31 Q0 SETUP Note: n depends on Burst X-Latency 1. For set up signals and timings see Synchronous Burst Read. Figure 18. Synchronous ...
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DC and AC parameters Figure 19. Synchronous Burst Read - burst address advance K VALID A0-A19 L DQ0-DQ31 G B Figure 20. Clock input AC waveform K 58/81 Q0 tGLQV tBLKH tKHKL tKLKH M58BW16F, M58BW32F Q1 Q2 tBHKH AI03650 ai13286 ...
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M58BW16F, M58BW32F Table 21. Synchronous Burst Read AC characteristics Symbol Parameter f Clock frequency t Address Valid to Valid Clock Edge, AVKH t Clock High Time KHKL t Clock Low Time KLKH Burst Address Advance High to Valid t BHKH ...
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DC and AC parameters Figure 21. Reset, Power-Down and Power-up AC waveform tVDHPH VDD, VDDQ Table 22. Reset, Power-Down and Power-up AC characteristics Symbol t Reset/Power-down High to Chip Enable Low PHEL (1) t Reset/Power-down ...
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M58BW16F, M58BW32F 8 Package mechanical In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box ...
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Package mechanical Table 23. LBGA80 10 × 12mm - 8 × 10 active ball array, 1mm pitch, package mechanical data Symbol 10.000 D1 ddd E 12.000 62/81 millimeters Typ ...
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M58BW16F, M58BW32F Figure 23. PQFP80 - 80 lead Plastic Quad Flat Pack, package outline Nd 1. Drawing is not to scale. Table 24. PQFP80 - 80 lead Plastic Quad Flat Pack, package mechanical data Symbol ...
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... Qualified & characterized according to AEC Q100 & Q003 or equivalent, advanced screening according to AEC Q001 & Q002 or equivalent. Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you ...
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... NO Program to Protect Block Error Flowcharts Program Command: – write 40h, Address AAh – write Address & Data (memory enters read status state after the Program command) do: – read status register ( must be toggled) while PEN invalid error: – error handler Program error: – ...
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... Program/Erase Suspend Command: – write B0h – write 70h do: – read status register while Program completed Read Memory Array Command: – write FFh – one or more data reads from other blocks Program Erase Resume Command: – write D0h to resume programming – ...
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... Erase to Protected Block Error Flowcharts Erase Command: – write 20h, Address 55h – write Block Address (A11-A19) & D0h (memory enters read status state after the Erase command) do: – read status register ( must be toggled) if Erase command given execute suspend erase loop ...
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... Program/Erase status bit Erase is completed (b6 = Erase Suspend status bit) The device returns to Read mode as normal (as if the Program/Erase Suspend was not issued). Read Memory Array command: – Write FFh – One or more data reads from other blocks Program/Erase Resume command: – ...
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M58BW16F, M58BW32F Figure 28. Power-up sequence followed by Synchronous Burst Read Power-up or Reset Asynchronous Read Write 60h command Write 03h with A15-A0 BCR inputs Synchronous Read BCR bit 15 = '1' Set Burst Configuration Register Command: – write 60h ...
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Flowcharts Figure 29. Command Interface and Program Erase Controller flowchart (a) WAIT FOR COMMAND WRITE NO 90h YES READ ELEC. 98h SIGNATURE READ CFI ERASE COMMAND ERROR READ STATUS B 70/81 NO YES NO 70h YES READ NO 20h STATUS ...
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M58BW16F, M58BW32F Figure 30. Command Interface and Program Erase Controller flowchart ( 48h YES TP 78h PROGRAM SET_UP F TP UNLOCK SET_UP G NO YES NO 60h YES NO FFh SET BCR SET_UP YES NO 03h YES Flowcharts ...
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Flowcharts Figure 31. Command Interface and Program Erase Controller flowchart ( READ STATUS READ ARRAY 72/81 YES ERASE SUSPENDED YES YES 70h NO YES PROGRAM 40h SET_UP NO NO YES READ D0h STATUS M58BW16F, M58BW32F A ERASE YES ...
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M58BW16F, M58BW32F Figure 32. Command Interface and Program Erase Controller flowchart ( READ STATUS READ ARRAY YES YES PROGRAM SUSPENDED YES YES 70h NO NO YES READ D0h STATUS Flowcharts C PROGRAM READY NO NO READ B0h STATUS ...
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Flowcharts Figure 33. Command Interface and Program Erase Controller flowchart (e) 74/ PROGRAM YES NO READ READY STATUS UNLOCK YES NO READ READY STATUS M58BW16F, M58BW32F AI03839 ...
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... Common Flash Interface (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary ...
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Common Flash Interface (CFI) Table 27. CFI - Query address and data output Address A0-Amax 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1. The x8 or Byte Address and the x16 or Word Address mode are ...
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... Address offset (P)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h (P+8)h Data n 15h 2 number of bytes memory size 03h Device Interface Sync./Async. 00h Organization Sync./Async. 00h Maximum number of Byte in multi-Byte program = 2 00h 02h Bit7-0 = number of Erase Block Regions in device 1Eh Number (n-1) of erase blocks of identical size; n=31 00h 00h Erase Block region information x 256 bytes per Erase ...
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... Unique Device (16 bits) 83h xxxx xxxxh Unique Device (16 bits) Data n 16h 2 number of bytes memory size 03h Device Interface Sync./Async. 00h Organization Sync./Async. 05h Page size in bytes, 2 00h 03h Bit7-0 = number of Erase Block Regions in device ...
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M58BW16F, M58BW32F Table 32. M58BW32F Extended query information Address offset (P)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h (P+8)h (P+9)h (P+A)h-(P+40)h (P+41)h (P+42)h (P+43)h (P+44)h Address Data (Hex) Amax-A0 39h 50 P 3Ah 52 R Query ASCII string - Extended ...
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Revision history Revision history Table 33. Document revision history Date 09-Jun-2006 23-Nov-2006 80/81 Revision 1 Initial release. V signal renamed as PEN and PEN modified. Continuous burst and wrap options are not available, X-Latencies 7 and 8 removed (see Table ...
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M58BW16F, M58BW32F Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein ...