HYB18T512160AC-37 INFINEON [Infineon Technologies AG], HYB18T512160AC-37 Datasheet

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HYB18T512160AC-37

Manufacturer Part Number
HYB18T512160AC-37
Description
512-Mbit Double-Data-Rate-Two SDRAM
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet
D a t a S h e e t , Rev. 1.13, M a i 2 00 4
HYB18T512[400/800/160]AC–[3.7/5]
HYB18T512[400/800/160]AF–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
DDR2 SDRAM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .

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HYB18T512160AC-37 Summary of contents

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HYB18T512[400/800/160]AC–[3.7/5] HYB18T512[400/800/160]AF–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM Rev. 1.13 ...

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The information in this document is subject to change without notice. Edition 2004-05 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2004. © All Rights Reserved. Attention please! The information herein is given to describe ...

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HYB18T512[400/800/160]AC–[3.7/5] HYB18T512[400/800/160]AF–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM Rev. 1.13 ...

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HYB18T512[400/800/160]A[C/F]–[3.7/5] Revision History: Rev. 1.13 Page Subjects (major changes since last revision) all initial release We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us ...

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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents I 6 Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics. 1.1 Features The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: ± • 1.8 V 0.1 V Power Supply ± 1.8 ...

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... HYB18T512400AC–5 x4 DDR2–400 3–3–3 HYB18T512800AC–5 x8 HYB18T512160AC–5 x16 HYB18T512400AC–3.7 x4 DDR2–533 4–4–4 HYB18T512800AC–3.7 x8 HYB18T512160AC–3.7 x16 HYB18T512400AF–5 x4 DDR2–400 3–3–3 HYB18T512800AF–5 x8 HYB18T512160AF–5 x16 HYB18T512400AF–3.7 x4 DDR2–533 4–4–4 HYB18T512800AF–3.7 x8 HYB18T512160AF– ...

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Pin Configuration The pin configuration of a DDR2 SDRAM is listed by function in Type columns are explained in Table 4 depicted in Figure 1 for 4, Figure 2 Table 3 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin ...

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Table 3 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type Address Signals 16 organization L2 BA0 I L3 BA1 – ...

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Table 3 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type D3 DQ11 I/O D1 DQ12 I/O D9 DQ13 I/O B1 DQ14 I/O B9 DQ15 I/O Data Strobe 4 8 organisations B7 DQS I/O A8 DQS I/O Data Strobe 8 ...

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Table 3 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type V E1, J9, M9, R1 PWR DD V E7, F2, F8, H2, PWR SSQ PWR SSDL V J3,N1,P9 PWR SS Not Connected 4/ 8 organizations L3,L7, ...

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... BA1 A12 NC 2. Ball position G1 is Not Connected and will be used V , for BA2 on 1-Gbit memory densities and higher DD 3. Ball position L8 is A13 for 512-Mbit and higher and is Not Connected on 256-Mbit 13 Overview DQS SSQ DDQ V ...

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... K L A12 DDL They are isolated on thedevice from and 5. Ball position G1 is Not Connected and will be used for BA2 on 1-Gbit memory densities and higher 6. Ball position L8 is A13 for 512-Mbit and higher and is Not Connected on 256-Mbit DQS ...

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... DQ3 SSQ REF SS CKE BA0 BA1 A12 NC 3. Ball position L1 will be used for BA2 on 1-Gbit memory densities and higher 15 Overview UDQS SSQ DDQ V UDQS DQ15 SSQ V V DQ8 DDQ DDQ V UDQ2 DQ13 SSQ V ...

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DDR2 Addressing Table 6 512 Mbit DDR2 Addressing Configuration Number of Banks Bank Address Auto-Precharge Row Address Column Address Number of Column Address Bits 11 Number of I/Os Page Size [Bytes] ’colbits’ 1) Refered Refered ...

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... Address Inputs: Provides the row address for Activate commands and the column address and Auto-Precharge bit A10 (=AP) for Read/Write commands to select one location out of the memory array in the respective bank. A10 (=AP) is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10=low) or all banks (A10=high) ...

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... Row-Address Latch & Decoder Bank Control Logic Row-Address MUX Refresh Counter Address Register 4 I/O 4 Internal Memory Banks device; it does not represent an actual circuit implementation unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals. 18 ...

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... Row-Address Latch & Decoder Bank Control Logic Row-Address MUX Refresh Counter Address Register 8 I/O 4 Internal Memory Banks device; it does not represent an actual circuit implementation unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals. 19 ...

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... Decoder Bank Control Logic Row-Address MUX Refresh Counter Address Register 16 I/O 4 Internal Memory Banks device; it does not represent an actual circuit implementation. 3. LDM, UDM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional LDQS and UDQS signals. ...

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Functional Description 2.1 Simplified State Diagram Initialization Sequence CKEL Precharge BL Writing_AP Write Writing CKEL Active PD Figure 7 Simplified State Diagram Note: This Simplified State Diagram is intended to provide a floorplan of ...

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Basic Functionality Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for the burst length of four or eight in a programmed sequence. Accesses begin with the registration of ...

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... Power-Down mode, where the DLL is disabled. Address bit A13 and all “higher” address bits have to be set to “low” for compatibility with other DDR2 memory products with higher memory densities. 23 Functional Description Follow OCD ...

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MR Mode Register Definition BA1 BA0 A13 A12 A11 reg. addr w 1) A13 is only available for 4 and 8 configuration. 1) Field Bits Type Description BL [2:0] w Burst Length Number of sequential ...

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DDR2 SDRAM Extended Mode Register Set (EMRS(1)) The Extended Mode Register EMRS(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, OCD program, ODT, DQS and output buffers disable, RQDS and RDQS enable. The ...

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... Hi-Z. “High” on BA0 and “low” for BA1 have to be set to access the EMRS(1). A13 and all “higher” address bits have to be set to “low” for compatibility with other DDR2 memory products with higher memory densities. Refer to Definition (BA[1: RDQS is enabled in 8 components, the DM function is disabled. RDQS is active for reads and don’ ...

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The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering Self-Refresh operation and is automatically re- ...

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Off-Chip Driver (OCD) Impedance Adjustment DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of the sequence. Every calibration mode command should be followed by “OCD calibration mode exit” before any other Start EMRS: ...

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Extended Mode Register Set for OCD impedance adjustment OCD impedance adjustment can be done using the following EMRS(1) mode. In drive mode all outputs are driven out by DDR2 SDRAM and drive of RDQS is dependent on EMRS(1) bit enabling ...

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For proper operation of adjust mode clocks and should be met Figure 10. Input data pattern for adjustment, DT[0:3] is CK, CK CMD ...

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... Double-Data-Rate-Two SDRAM the ODT control pin. UDQS and LDQS are terminated only when enabled in the EMRS(1) by address bit A10 = 0. The ODT feature is designed to improve signal integ- rity of the memory channel by allowing the DRAM con- troller to independently resistance for any or all DRAM devices. ...

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ODT Truth Tables The ODT Truth Table shows which of the input pins are terminated depending on the state of address bit A10 and A11 in the EMRS(1) for all three device Table 11 ODT Truth Table Input Pin EMRS(1) ...

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CK, CK see note 1 CKE t ODT IS tAOND (2 tck) DQ Figure 13 ODT Timing for Active and Standby (Idle) Modes Note: 1. Synchronous ODT timings apply for Active Mode and Standby Mode with ...

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Mode entry: As long as the timing parameter when ODT is turned on or off before entering these power-down modes, synchronous timing parameters T- 5 CK, CK CKE ODT turn-off, tANPD >= 3 tCK : ODT ODT turn-off, tANPD <3 ...

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Mode exit: As long as the timing parameter when ODT is turned on or off after exiting these power- down modes, synchronous timing parameters can CK CKE ODT turn-off, tAXPD >= tAXPDmin: ...

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... A single Read or Write Command will initiate a serial read or write operation on successive clock cycles at data rates 667 Mb/sec/pin for main memory. The boundary of the burst cycle is restricted to specific segments of the page length. For example, the 32Mbit 4 I/O page length of 2048 bits (defined by CA[9:0] & ...

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Read or Write Command (CA[9:0] & CA11). A new burst access must not interrupt the previous 4 bit burst operation in case setting. Therefore the ...

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... RCDmin 2.6.2 Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst Data Sheet HYB18T512[400/800/160]A[C/F]– ...

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MRS. Seamless burst read or write operations are supported. Interruption of a burst read or write operation is prohibited, when burst length = 4 is programmed. For burst interruption of a read or Table ...

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CLK CLK, CLK CLK DQS, DQS DQ Figure 23 Basic Read Timing Diagram CK, CK Post CAS CMD NOP READ A DQS, DQS Figure 24 Burst Operation Example ...

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CK NOP D READ A DQS, DQS DQ Figure 25 Read Operation Example ( ...

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... The time from the completion of the burst write to bank precharge is named “write recovery time” and is the time needed to store the write data into WR the memory array. (see AC & DC Operating programmed value for WR in the MRS. 42 Functional Description T ...

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DQS, DQS Figure 29 Basic Write Timing ...

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rite 1 ...

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... insure matched system timing. Data mask is not used during read cycles high during a write burst coincident with the write data, the write data bit is not written to the memory. For 8 components the DM function is disabled, when RDQS / RDQS are enabled by EMRS(1). t ...

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<= tDQSS RL DIN A0 DIN A1 D ...

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Figure 37 Read Interrupt Timing Example 1: (CL ...

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Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the ...

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clks ...

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clo cks ...

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Write followed by Precharge Minimum Write to Precharge command spacing to the t same bank = For write cycles, a delay WR must be satisfied from the completion of the last burst write cycle ...

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... Commands.The precharge operation engaged by the Auto-Precharge command will not begin until the last data of the write burst sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon CAS Latency) thus improving system performance for random data access ...

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ste A10 ="high" BL ...

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ste A10 ="high" ...

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Write with Auto-Precharge If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM automatically begins precharge operation after the completion of the write burst plus the write recovery time ...

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Read or Write to Precharge Command Spacing Summary The following table summarizes the minimum command delays between Read, Read w/AP, Write, Table 14 Minimum Command Delays From Command To Command READ PRECHARGE (to same banks as READ) PRECHARGE-ALL READ ...

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Concurrent Auto-Precharge DDR2 devices support the “Concurrent Auto- Precharge” feature. A Read with Auto-Precharge enabled Write with Auto-Precharge enabled, may be followed by any command to the other bank, as long as that command does not interrupt ...

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CK, CK "high" CKE > CMD Figure 52 Auto Refresh Timing 2.9.2 Self-Refresh Command The Self-Refresh command can be used to retain data, even ...

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CK/CK CKE tis tAOFD ODT CMD Figure 53 Self Refresh Timing Note: 1. Device must be in the “All banks idle” state before entering Self Refresh mode. ( 200 ) has to be satisfied for a Read ...

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Power-Down Entry Active Power-down mode can be entered after an Activate command. Precharge Power-down mode can be entered after a Precharge, Precharge-All or internal precharge command also allowed to enter power- mode after an Auto-Refresh command or MRS ...

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...

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T0 T1 CK, CK CMD NOP Precharge tIS CKE tRP Precharge Power-Down Entry Figure 58 Precharge Power Down Mode Entry and Exit Note: "Precharge" may be an external command or an internal precharge following Write with AP ...

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Other Commands 2.11.1 No Operation Command The No Operation Command (NOP) should be used in cases when the SDRAM idle or a wait state. The purpose of the No Operation Command is to prevent the SDRAM ...

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... Asynchronous Low Reset Event Data Sheet HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM contents of the memory array. If this event occurs, the memory controller must satisfy a time delay ( before turning off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised “high” again. ...

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Truth Tables Table 16 Command Truth Table Function CKE Previous Cycle (Extended) Mode H Register Set Auto-Refresh H Self-Refresh Entry H Self-Refresh Exit L Single Bank Precharge H Precharge all Banks H Bank Activate H Write H Write with ...

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Table 17 Clock Enable (CKE) Truth Table for Synchronous Transitions 1) Current State CKE Previous Cycle (N-1) Power-Down L L Self Refresh L L Bank(s) H Active All Banks Idle H H Any State other H than listed above 1) ...

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Operating Conditions Table 19 Absolute Maximum Ratings Symbol Parameter V Voltage on V pin relative Voltage on V pin relative to DDQ DDQ V Voltage on VDDL pin relative to DDL Voltage ...

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AC & DC Operating Conditions 5.1 DC Operating Conditions Table 21 Recommended DC Operating Conditions (SSTL_18) Symbol Parameter V Supply Voltage DD V Supply Voltage for DLL DDDL V Supply Voltage for Output DDQ V Input Reference Voltage REF ...

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DC & AC Logic Input Levels DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system ...

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Table 26 Differential DC and AC Input and Output Logic Levels Symbol Parameter V DC input signal voltage IN(dc differential input voltage ID(dc differential input voltage ID( differential cross point input IX(ac) voltage ...

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Output Buffer Table 27 SSTL_18 Output AC Test Conditions Symbol Parameter V Minimum Required Output Pull- Maximum Required Output Pull-down OL V Output Timing Measurement Reference Level OTR V 1) SSTL_18 test load for and OH VOL ...

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Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQ’s is included and specification. DQSQ QHS 8) DRAM output slew rate specification applies to 400, 533 and 667 MT/s speed ...

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Figure 65 Full Strength Default Pull-up Driver Diagram Table 31 Full Strength Default Pull–down Driver Characteristics Voltage (V) Pull-down Driver Current [mA] Minimum 0.2 8.5 0.3 12.1 0.4 14.7 0.5 ...

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Figure 66 Full Strength Default Pull–down Driver Diagram 5.4.1 Calibrated Output Driver V-I Characteristics DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the ...

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Table 32 Full Strength Calibrated Pull-down Driver Characteristics Voltage (V) Calibrated Pull-down Driver Current [mA] Nominal Minimum (21 Ohms) 0.2 9.5 0.3 14.3 0.4 18.7 Note: The driver characteristics evaluation conditions are Nominal ...

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Power & Ground Clamp V-I Characteristics Power and Ground clamps are provided on address (A[13:0], BA[1:0]), RAS, CAS, CS, WE, CKE and ODT Table 35 Power & Ground Clamp V-I Characteristics Voltage across clamp (V) 0.0 0.1 0.2 0.3 ...

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Specifications and Conditions Table 36 Measurement Conditions DD Parameter Operating Current 0 One bank Active - Precharge high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING . Operating Current ...

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I Table 36 Measurement Conditions DD Parameter Self-Refresh Current CKE 0.2 V; external clock off, CK and Other control and address inputs are FLOATING, Data bus inputs are FLOATING. RESET = Low. guaranteed ...

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Test Conditions I DD For testing the I parameters, the following timing parameters are used: DD Table 38 IDD Measurement Test Condition Parameter CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active / Auto-Refresh ...

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Electrical Characteristics & AC Timing - Absolute Specification Table 40 Timing Parameter by Speed Grade - DDR2-400 & DDR2-533 Symbol Parameter t DQ output access time from DQS output access time from CK / ...

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Table 40 Timing Parameter by Speed Grade - DDR2-400 & DDR2-533 Symbol Parameter t Auto-Refresh to Active/Auto-Refresh RFC command period t Active to Read or Write delay RCD (with and without Auto-Precharge) t Precharge command period RP t Active bank ...

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10 & 5 11) For timing definition, slew rate and slew rate derating see 12) For timing definition, slew rate and slew rate derating see 13) The , and , ...

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Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating 8.1 Reference Load for Timing Measurements The figure represents the timing reference load used in defining the relevant timing parameters of the device not intended to ...

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Input and Data Setup and Hold Time 8.3.1 Timing Definition for Input Setup ( Address and control input setup time ( from the input signal crossing at the V rising signal and for a falling signal applied to the ...

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DQS DQS DQS Figure 69 Data, Setup and Hold Time Diagram 8.3.3 Slew Rate Definition for Input and Data Setup and Hold Times Setup ( t ) nominal slew rate for a rising signal is DS defined as the slew ...

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CK,DQS CK,DQS V DDQ V min IH (ac) V min IH (dc) V REF(dc) V max IL (dc) V max IL (ac Figure 70 Slew Rate Definition Nominal Diagram for Note: DQS, DQS signals must be monotonic between ...

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CK,DQS CK,DQS V DDQ V IH (ac) min V min IH (dc) V REF V max IL (dc (ac) max Nominal line V SS Figure 71 Slew Rate Definition Tangent Diagram for Note: DQS, DQS signals must be ...

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CK ,DQS CK ,DQS V DDQ V IH (ac) min V min IH (dc) V REF(dc (dc) max V IL (ac) max V SS Figure 72 Slew Rate Definition Nominal Diagram for Note: DQS, DQS signals must be ...

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CK,DQS CK,DQS V DDQ V IH (ac) min V min IH (dc) V REF(dc (dc) max V IL (ac) max V SS Figure 73 Slew Rate Definition Tangent Diagram for Note: DQS, DQS signals must be monotonic between ...

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Table 42 Input Setup ( t ) and Hold ( IS Command / Address Slew rate (V/ns) CK, CK Differential Slew Rate 2.0 V/ 4.0 187 3.5 179 3.0 167 2.5 150 2.0 125 1.5 83 1.0 0 ...

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Table 43 Data Setup ( t ) and Hold Time ( DS DQS, DQS Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ 2.0 125 45 125 45 125 45 ...

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Table 45 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area above Maximum undershoot area below VDDQ VSSQ Figure ...

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Package Dimensions 1) 1) Dummy pads without ball 2) Middle of packages edges 3) Package orientation mark A1 4) Bad unit marking (BUM) 5) Die sort fiducial Figure 76 Package Pinout P-TFBGA-60-6 (top view) Data Sheet HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two ...

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Dummy pads without ball 2) Middle of packages edges 3) Package orientation mark A1 4) Bad unit marking (BUM) 5) Die sort fiducial Figure 77 Package Pinout P-TFBGA-84-1 (top view) Data Sheet HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM 12.5 14 ...

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DDR2 Component Nomenclature Table 46 Nomenclature Fields and Examples Example for Field Number 1 2 DDR2 DRAM HYB 18 Table 47 DDR2 DRAM Nomenclature Field Description 1 INFINEON Component Prefix 2 Interface Voltage [V] 3 DRAM Technology 4 Component ...

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Published by Infineon Technologies AG ...

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