HYB18T512400BF QIMONDA [Qimonda AG], HYB18T512400BF Datasheet
HYB18T512400BF
Related parts for HYB18T512400BF
HYB18T512400BF Summary of contents
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– – B HYS72T128420HFA–[2.5/3S/3.7]–B HYS72T256420HFA–[2.5/3S/3.7]– ...
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Revision History: Rev.1.01, 2007-06-20 Page 5 Added product type to Previous Revision: Rev. 1.00, 2006-10-06 All Converted to QAG template We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? ...
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... This chapter describes the main characteristics of the 240-Pin Fully-Buffered DDR2 SDRAM Modules product family. 1.1 Features • 240-pin Fully-Buffered ECC Dual-In-Line DDR2 SDRAM Module for PC, Workstation and Server main memory applications. • One rank 64M × 72 and , two rank 128M × 72, 256M × 72 module organization, and 64M × 8, 128M × 4 chip organization • ...
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... Fully Buffered Double-Data-Rate Two Synchronous DRAM Dual In-Line Memory Modules (DDR2 SDRAM FB-DIMMs). Fully Buffered DIMMs use commodity DRAMs isolated from the memory channel behind a buffer on the DIMM. They are intended for use as main memory when installed in systems such as servers and workstations. PC2-4200F, PC2-5300F, ...
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... Product Type DRAM Components HYS72T256020HFA HYB18T512400BF HYS72T128020HFA HYB18T512800BF HYS72T64400HFA HYB18T512800BF 1) Green Product 2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet. Rev.1.01, 2007-06-20 10062006-RQWY-GI6S HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B ...
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Pin Configuration The pin configuration of the DDR2 SDRAM DIMM is listed by function in Pin and Buffer Type are explained in Table 6 Pin# Nam Pin Buffer e Type Type Clock Signals 228 SCK I HSDL_15 229 SCK ...
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Pin# Nam Pin Buffer e Type Type 67 PN11 O HSDL_15 49 PN12 O HSDL_15 41 PN13 O HSDL_15 142 SN0 I HSDL_15 145 SN1 I HSDL_15 148 SN2 I HSDL_15 151 SN3 I HSDL_15 154 SN4 I HSDL_15 157 ...
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Pin# Nam Pin Buffer e Type Type 102 PS8 I HSDL_15 90 PS9 I HSDL_15 71 PS0 I HSDL_15 74 PS1 I HSDL_15 77 PS2 I HSDL_15 80 PS3 I HSDL_15 83 PS4 I HSDL_15 94 PS5 I HSDL_15 97 ...
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Pin# Nam Pin Buffer e Type Type 238 V PWR – DDSP D 9,10,12,13,1 V PWR – CC 29,130,132, 133 15,117,135, V PWR – TT 237 1,2,3,5,6,7,1 V PWR – DD 08,109,111, 112,113,115 ,116,121,12 2,123,125,1 26, 127,231,232 ,233,235,23 6 4,8,11,14,18 ...
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Pin# Nam Pin Buffer e Type Type 19,20,44,45, RFU NC – 86,87,105,1 06,139, 140,164,165 ,206,207,22 5,226 136 VID0 – – 16 VID1 – – 137 Test AI – Abbreviation Description HSDL_15 High-Speed Differential Point-to-Point Link Interface at 1.5 V LV-CMOS ...
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Rev.1.01, 2007-06-20 10062006-RQWY-GI6S HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B Fully-Buffered DDR2 SDRAM Modules Pin Configuration for FB-DIMM (240 pin) 11 Internet Data Sheet FIGURE 1 ...
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... Basic Functionality This chapter describes the basic functionality. 3.1 Advanced Memory Buffer Overview The Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol Specification. 3.2 Advanced Memory Buffer Functionality The Advanced Memory Buffer will perform the following FB- DIMM channel functions: • ...
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... HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B Fully-Buffered DDR2 SDRAM Modules Block Diagram Advanced Memory Buffer Interface last DIMM receives the data. The last DIMM in the chain initiates the transmission of data in the direction of the host (a.k.a. northbound). On the northbound data path each DIMM receives the data and re-drives the data to the next DIMM until the host is reached ...
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... FB-DIMM link. The Advanced Memory Buffer will never be a master on the SMBus, only a slave. Serial SMBus data transfer is supported at 100 kHz. SMBus access to the Advanced Memory Buffer may be a requirement to boot and 3.4.3 Channel Latency FB-DIMM channel latency is measured from the time a read ...
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Peak Theoretical Channel Throughput An FB-DIMM channel transfers read completion data on the Northbound data connection. 144 bits of data are transferred for every Northbound data frame. This matches the 18-byte data transfer of an ECC DDR DRAM in ...
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Electrical Characteristics This chapter describes the electrical characteristics. 4.1 Operating Conditions This chapter describes the operating conditions. Symbol Parameter V V Voltage on pin relative Voltage on pin relative ...
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Parameter AMB Supply Voltage DRAM Supply Voltage Termination Voltage EEPROM Supply Voltage DC Input Logic High(SPD) DC Input Logic Low(SPD) DC Input Logic High(RESET) DC Input Logic Low(RESET) Leakage Current (RESET) Leakage Current (Link) 1) Applies for SMB and SPD ...
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Parameter Operating Temperature Operating Humidity (relative) Storage Temperature Storage Humidity (without condensation) Barometric pressure (operating) Barometric pressure (storage) 1) The designer must meet the case temperature specifications for individual module components. 2) Stresses greater than those listed may cause permanent ...
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Current Spec. and Conditions The following table provides an overview of the measurement conditions. Parameter Idle Current, single or last DIMM L0 state, idle (0 BW) Primary channel enabled, Secondary channel disabled CKE high. Command and address lines stable. ...
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Address and Data fields provide toggle rate on DRAM data and link lanes. 4. Burst Length = lanes southbound and 14 lanes northbound are enabled and active (12 lanes NB if non-ECC DIMM). ...
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I I 5.1 / Conditions the following table you can find the Measurement Conditions and Power Supply Currents Note: Conditions for 2.5 has TBD Product Type Speed Grade PC2-5300F Symbol Typ. I 1.65 CC_Idle_0 P 2.51 CC_Idle_0 ...
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Product Type Speed Grade PC2-5300F Symbol Typ. P 1.17 DD_Active_2 I 3.42 TOT_Active_2 P 5.3 TOT_Active_2 I 3.21 CC_IBIST P 4.79 CC_IBIST I 0.65 DD_IBIST P 1.14 DD_IBIST I 3.86 TOT_IBIST P 5.94 TOT_IBIST I 2.99 CC_Training P 4.47 CC_Training ...
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Product Type Speed Grade PC2-4200F Symbol Typ. I 1.49 CC_Idle_0 P 2.27 CC_Idle_0 I 0.79 DD_Idle_0 P 1.4 DD_Idle_0 I 2.29 TOT_Idle_0 P 3.67 TOT_Idle_0 I 2.41 CC_Idle_1 P 3.63 CC_Idle_1 I 0.79 DD_Idle_1 P 1.4 DD_Idle_1 I 3.22 TOT_Idle_1 ...
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Product Type Speed Grade PC2-4200F Symbol Typ. I 3.5 TOT_IBIST P 5.39 TOT_IBIST I 2.68 CC_Training P 4.03 CC_Training I 0.6 DD_Trainig P 1.06 DD_Training I 3.33 TOT_Trainig P 5.13 TOT_Training I 1.85 CC_EI P 2.79 CC_EI I 0.09 DD_EI ...
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SPD Codes This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 13 CAS Latencies Supported t 14 (min. CAS Latency Time) CAS.MIN 15 Write Recovery Values Supported (WR (Write Recovery Time) WR.MIN 17 Write Latency Times Supported 18 Additive ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description ∆ T (DT4R) / ∆ Sign (DT4R4W) DRAM 4R 4R4W ∆ (DT5B) DRAM 5B ∆ (DT7) DRAM Not used 79 ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 104 AMB Personality Bytes: Pre-initialization (4) 105 AMB Personality Bytes: Pre-initialization (5) 106 AMB Personality Bytes: Pre-initialization (6) 107 AMB Personality Bytes: Post-initialization (1) 108 AMB Personality Bytes: Post-initialization (2) ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 132 Module Product Type, Char #5 133 Module Product Type, Char #6 134 Module Product Type, Char #7 135 Module Product Type, Char #8 136 Module Product Type, Char #9 ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 SPD Size CRC / Total / Used 1 SPD Revision 2 Key Byte / DRAM Device Type 3 Voltage Level of this Assembly 4 SDRAM Addressing 5 Module Physical ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 23 (min. Active to Precharge Time) RAS.MIN t 24 (min. Active to Active / Refresh Time) RC.MIN t 25 LSB (min. Refresh Recovery Time Delay) RFC.MIN t 26 MSB ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 85 AMB Read Access Delay for DDR2-667 86 AMB Read Access Delay for DDR2-533 87 Psi(T-A) AMB ∆ (DT Idle_0) AMB Idle_0 ∆ (DT Idle_1) AMB ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 114 AMB Personality Bytes: Post-initialization (8) 115 AMB Manufacturers JEDEC ID Code LSB 116 AMB Manufacturers JEDEC ID Code MSB 117 DIMM Manufacturers JEDEC ID Code LSB 118 DIMM Manufacturers ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 142 Module Product Type, Char #15 143 Module Product Type, Char #16 144 Module Product Type, Char #17 145 Module Product Type, Char #18 146 Module Revision Code 147 Test ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 SPD Size CRC / Total / Used 1 SPD Revision 2 Key Byte / DRAM Device Type 3 Voltage Level of this Assembly 4 SDRAM Addressing 5 Module Physical ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 23 (min. Active to Precharge Time) RAS.MIN t 24 (min. Active to Active / Refresh Time) RC.MIN t 25 LSB (min. Refresh Recovery Time Delay) RFC.MIN t 26 MSB ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 85 AMB Read Access Delay for DDR2-667 86 AMB Read Access Delay for DDR2-533 87 Psi(T-A) AMB ∆ (DT Idle_0) AMB Idle_0 ∆ (DT Idle_1) AMB ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 114 AMB Personality Bytes: Post-initialization (8) 115 AMB Manufacturers JEDEC ID Code LSB 116 AMB Manufacturers JEDEC ID Code MSB 117 DIMM Manufacturers JEDEC ID Code LSB 118 DIMM Manufacturers ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 142 Module Product Type, Char #15 143 Module Product Type, Char #16 144 Module Product Type, Char #17 145 Module Product Type, Char #18 146 Module Revision Code 147 Test ...
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Package Outline All Components are surface mounted on one or both sides of the PCB and positioned on the PCB to meet the minimum and maximum trace lengths required for DDR2 SDRAM signals. PCB L-DIM-240-21 Figure 4 L-DIM-240-22 Figure ...
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Rev.1.01, 2007-06-20 10062006-RQWY-GI6S HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B Fully-Buffered DDR2 SDRAM Modules Package Outline L-DIM-240-21 with Full Module Heat Sink 41 Internet Data Sheet FIGURE 4 ...
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Rev.1.01, 2007-06-20 10062006-RQWY-GI6S HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B Fully-Buffered DDR2 SDRAM Modules Package Outline L-DIM-240-22 with Full Module Heat Sink 42 Internet Data Sheet FIGURE 5 ...
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Rev.1.01, 2007-06-20 10062006-RQWY-GI6S HYS72T[64/128/256]4[00/20]HFA–[2.5/3S/3.7]–B Fully-Buffered DDR2 SDRAM Modules Package Outline L-DIM-240-25 with Full Module Heat Sink 43 Internet Data Sheet FIGURE 6 ...
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... Field Number 1 2 Micro-DIMM HYS 64 DDR2 DRAM HYB 18 Field Description 1 Module Prefix 2 Module Data Width [bit] 3 DRAM Technology 4 Memory Density per I/O [Mbit]; 1) Module Density 5 Raw Card Generation 6 Number of Module Ranks 7 Product Variations 8 Package, Lead-Free Status 9 Module Type 10 Speed Grade Rev.1.01, 2007-06-20 10062006-RQWY-GI6S HYS72T[64/128/256]4[00/20]HFA– ...
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... Field Description 11 Die Revision 1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column “Coding”. Field Description 1 Component Prefix 2 Interface Voltage [V] 3 DRAM Technology ...
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... Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Basic Functionality 3.1 Advanced Memory Buffer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Advanced Memory Buffer Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.1 DDR2 Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.2 SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.3 Channel Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.4 Peak Theoretical Channel Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 Hot-add 3.6 Hot-remove 3.7 Hot-replace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 Electrical Characteristics ...
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Edition 2007-06-20 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or ...