HYB18T512400BF-2.5 QIMONDA [Qimonda AG], HYB18T512400BF-2.5 Datasheet
HYB18T512400BF-2.5
Related parts for HYB18T512400BF-2.5
HYB18T512400BF-2.5 Summary of contents
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HYB18T512400B[C/F], HYB18T512160B[C/F], HYB18T512800B[C/F] Revision History: 2007-05, Rev. 1.1 Page Subjects (major changes since last revision) All Adapted internet edition All Added more product types Previous Revision: 2007-01, Rev. 1.05 All Qimonda template update Previous Revision: 2006-02, Rev. 1.04 We Listen ...
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Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics. 1.1 Features The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: ± • 1.8 V 0.1 V Power Supply ± 1.8 ...
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Product Type Speed Code Speed Grade f Max. Clock Frequency @CL5 CK5 f @CL4 CK4 f @CL3 CK3 t Min. RAS-CAS-Delay RCD t Min. Row Precharge Time RP t Min. Row Active Time RAS t Min. Row Cycle Time RC ...
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Description The 512-Mb DDR2 DRAM is a high-speed Double-Data- Rate-Two CMOS DRAM device containing 536,870,912 bits and is internally configured as an quad-bank DRAM. The 512-Mb device is organized as either 32 Mbit × 4 I/O ×4 banks, 16 ...
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... Product Type Org. Speed ×4 HYB18T512400BF-2.5 DDR2-800E 6-6-6 ×8 HYB18T512800BF-2.5 DDR2-800E 6-6-6 ×16 HYB18T512160BF-2.5 DDR2-800E 6-6-6 HYB18T512400BF-25F ×4 DDR2- 800D HYB18T512800BF-25F ×8 DDR2- 800D HYB18T512160BF-25F ×16 DDR2- 800D ×4 HYB18T512400BF-3S DDR2- 667D ×8 HYB18T512800BF-3S DDR2- 667D ×16 HYB18T512160BF-3S DDR2- 667D ×4 HYB18T512400BF-3 DDR2- 667C × ...
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Product Type Org. Speed ×8 HYB18T512800BC-3S DDR2-667D ×16 HYB18T512160BC-3S DDR2-667D ×8 HYB18T512800BC-3.7 DDR2-533C ×16 HYB18T512160BC-3.7 DDR2-533C 1) CAS: Column Address Strobe 2) RCD: Row Column Delay 3) RP: Row Precharge Note: For product nomenclature see Chapter 9 Rev. 1.1, 2007-05 ...
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Chip Configuration This chapter contains the chip configuration and addressing. 2.1 Chip Configuration The chip configuration of a DDR2 SDRAM is listed by function in columns are explained in Table 8 and Table 9 for ×4, for ×8 and ...
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Ball# Name Ball Type A10 ...
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Ball# Name Ball Type D1 DQ4 I/O D9 DQ5 I/O B1 DQ6 I/O B9 DQ7 I/O Data Signals ×16 organization G8 DQ0 I/O G2 DQ1 I/O H7 DQ2 I/O H3 DQ3 I/O H1 DQ4 I/O H9 DQ5 I/O F1 DQ6 ...
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Ball# Name Ball Type V A1 PWR DD V A7, B2, B8, D2, PWR SSQ D8 V A3, E3 PWR SS Power Supplies ×4/×8 organizations REF V E1 PWR DDL V E9, H9, L1 PWR DD V ...
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Abbreviation Description I Standard input-only ball. Digital levels. O Output. Digital levels. I/O I bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NC Not Connected Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL_18) LV-CMOS Low ...
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Notes and are power and ground for the DLL. DDL SSDL V V connected to on the device and are isolated on the device. SSQ Rev. 1.1, 2007-05 03292006-YBYM-WG0Z 512-Mbit Double-Data-Rate-Two SDRAM Chip Configuration ...
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Notes 1. RDQS / RDQS are enabled by EMRS(1) command RDQS / RDQS is enabled, the DM function is disabled 3. When enabled, RDQS & RDQS are used as strobe signals during reads. Rev. 1.1, 2007-05 03292006-YBYM-WG0Z 512-Mbit ...
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Notes 1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0] Rev. 1.1, 2007-05 03292006-YBYM-WG0Z 512-Mbit Double-Data-Rate-Two SDRAM Chip Configuration for ×16 components, PG-TFBGA-84 (top view) 2. LDM is the data mask signal for DQ[7:0], UDM is ...
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Addressing This chapter describes the addressing. Configuration Bank Address Number of Banks Auto-Precharge Row Address Column Address Number of Column Address Bits Number of I/Os Page Size [Bytes] 1) Referred to as ’org’ 2) Referred to as ’colbits’ colbits ...
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Configuration Bank Address Number of Banks Auto-Precharge Row Address Column Address Number of Column Address Bits Number of I/Os Page Size [Bytes] 1) Referred to as ’org’ 2) Referred to as ’colbits’ colbits × org/8 [Bytes] 3) PageSize = 2 ...
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Functional Description This chapter contains the functional description. 1) Field Bits Type Description BA2 16 reg. addr. Bank Address [2] Note: BA2 not available on 256 Mbit and 512 Mbit components 0 B BA1 15 Bank Address [1] 0 ...
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Field Bits Type Description CL [6:4] w CAS Latency Note: All other bit combinations are illegal. 011 B 100 B 101 B 110 B 111 Burst Type [2:0] w Burst ...
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Field Bits Type Description DQS 10 w Complement Data Strobe (DQS Output OCD [9:7] w Off-Chip Driver Calibration Program Program 000 B 001 B 010 B 100 B 111 B AL [5:3] w Additive Latency ...
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EMRS(2) Programming Extended Mode Register Definition (BA[2:0]=010 1) Field Bits Type Description BA [15:14] w Bank Adress 00 BA MRS EMRS( EMRS( EMRS(3): Reserved B SRF 7 w Address Bus, High ...
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EMR(3) Programming Extended Mode Register Definition(BA[2:0]=011 1) Field Bits Type Description BA2 16 reg.addr Bank Address[2] Note: BA2 is not available on 256 Mbit and 512 Mbit components 0 BA2 Bank Address B BA1 15 Bank Adress[1] 1 BA1 Bank ...
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Input Pin ×4 Components DQ[3:0] DQS DQS DM ×8 Components DQ[7:0] DQS DQS RDQS RDQS DM ×16 Components DQ[7:0] DQ[15:8] LDQS LDQS UDQS UDQS LDM UDM Note don’t care bit set to low bit ...
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Burst Length Starting Address (A2 A1 A0) × × ×1 0 × ...
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Truth Tables The truth tables in this chapter summarize the commands and there signal coding to control a standard Double-Data-Rate-Two SDRAM. Function CKE Previous Cycle (Extended) Mode H Register Set Auto-Refresh H Self-Refresh Entry H Self-Refresh Exit L Single ...
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Current State CKE 6) Previous Cycle (N-1) Power-Down L L Self Refresh L L Bank(s) Active H All Banks Idle H H Any State other H than listed above 1) Current state is the state of the DDR2 SDRAM ...
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Electrical Characteristics This chapter describes the electrical characteristics. 5.1 Absolute Maximum Ratings Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Symbol Parameter V V Voltage on pin relative ...
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DC Characteristics Symbol Parameter V Supply Voltage DD V Supply Voltage for DLL DDDL V Supply Voltage for Output DDQ V Input Reference Voltage REF V Termination Voltage tracks with , tracks with ...
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DC & AC Characteristics DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The ...
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Symbol Parameter V DC input signal voltage IN(dc differential input voltage ID(dc differential input voltage ID(ac differential cross point input voltage IX(ac differential cross point output voltage 0.5 × OX(ac ...
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Output Buffer Characteristics This chapter describes the Output Buffer Characteristics. Symbol Parameter I Output Minimum Source DC Current OH I Output Minimum Sink DC Current 1 1. – ...
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Symbol Description — Output Impedance — Pull-up / Pull down mismatch — Output Impedance step size for OCD calibration S Output Slew Rate OUT V ± V ± 1 1.8 V 0.1 V DDQ ...
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Input / Output Capacitance This chapter contains the input / output capacitance. Symbol Parameter CCK Input capacitance, CK and CK CDCK Input capacitance delta, CK and CK CI Input capacitance, all other input-only pins CDI Input capacitance delta, all ...
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Symbol Parameter CCK Input capacitance, CK and CK CDCK Input capacitance delta, CK and CK CI Input capacitance, all other input-only pins CDI Input capacitance delta, all other input-only pins CIO Input/output capacitance, DQ, DM, DQS, DQS, RDQS, RDQS CDIO ...
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Overshoot and Undershoot Specification This chapter contains overshoot and undershoot specification. AC Overshoot / Undershoot Specification for Address and Control Pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area V Maximum overshoot ...
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AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins Rev. 1.1, 2007-05 03292006-YBYM-WG0Z HYB18T512[40/80/16]0B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM 36 Internet Data Sheet FIGURE 7 ...
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Currents Measurement Conditions This chapter describes the current measurement specifications and conditions. Parameter Operating Current - One bank Active - Precharge CK(IDD) RC RC(IDD) RAS RAS.MIN(IDD) Address ...
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Parameter Self-Refresh Current CKE ≤ 0.2 V; external clock off, CK and Other control and address inputs are floating, Data bus inputs are floating. Operating Bank Interleave Read Current I 1. All banks interleaving reads, = ...
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DDR2-800D DDR2-800E Symbol Max. Max. IDD0 84 80 105 100 IDD1 100 95 120 115 IDD2P 7 7 IDD2N 51 51 IDD2Q 45 45 IDD3P IDD3N 60 60 IDD4R 155 155 180 180 IDD4W ...
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Timing Characteristics This chapter contains speed grade definition, AC timing parameter and ODT tables. 7.1 Speed Grade Definitions All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications ( Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock ...
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Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time 1) imings are guaranteed with CK/CK differential Slew ...
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V 3) Inputs are not recognized as valid until 4) The output timing reference voltage level calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to ...
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Component AC Timing Parameters List of Timing Parameters Tables. Parameter DQ output access time from CAS to CAS command delay Average clock high pulse width Average clock period CKE minimum pulse width ( high and low ...
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Parameter Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Precharge-All (8 banks) command period Read preamble Read postamble Internal Read to Precharge command delay Write preamble Write postamble Write recovery time Internal write to ...
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DAL = WR + RU{ (ns) / (ns)}, where RU stands for round up. WR refers to the the division is not already an integer, round up to the next highest integer ...
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When the device is operated with input clock jitter, this parameter needs to be derated by the actual deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t t ...
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Parameter Mode register set command cycle time OCD drive mode output delay DQ/DQS output hold time from DQS DQ hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Read preamble Read postamble ...
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These parameters are specified per their average values, however it is understood that the relationship as defined in the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be ...
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When the device is operated with input clock jitter, this parameter needs to be derated by the actual deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t t ...
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Rev. 1.1, 2007-05 03292006-YBYM-WG0Z HYB18T512[40/80/16]0B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM Method for calculating transitions and endpoint Differential input waveform timing - t Differential input waveform timing - 50 Internet Data Sheet FIGURE 8 FIGURE 9 and FIGURE 10 t ...
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Parameter DQ output access time from CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks ...
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Parameter Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Active bank A to Active bank B command period Internal Read to ...
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The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C and 95 °C. 14) 0 °C ≤ T ≤ 85 °C CASE 15) 85 °C < T ...
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Parameter Clock half period Data-out high-impedance time from Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from DQS low-impedance ...
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Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended ...
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Jitter Definition and Clock Jitter Specification Generally, jitter is defined as “the short-term variation of a signal with respect to its ideal position in time”. The following table provides an overview of the terminology. Symbol Parameter t Average clock ...
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Symbol Parameter t Cumulative error ERR.nPER across n cycles t Average high-pulse CH.AVG width t Average low-pulse CL.AVG width t Duty-cycle jitter JIT.DUTY Rev. 1.1, 2007-05 03292006-YBYM-WG0Z 512-Mbit Double-Data-Rate-Two SDRAM Description t is defined as the cumulative error across n ...
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The following parameters are specified per their average values however understood that the following relationship between the average timing and the absolute instantaneous timing holds all the time. Symbol Parameter Min Clock period CK.ABS t t ...
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ODT AC Electrical Characteristics This chapter describes the ODT AC electrical characteristics. ODT AC Characteristics and Operating Conditions for DDR2-533 and DDR2-400 Symbol Parameter / Condition t ODT turn-on delay AOND t ODT turn-on AON t ODT turn-on (Power-Down ...
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Package Dimensions This chapter describes the package dimensions. Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.1, 2007-05 03292006-YBYM-WG0Z HYB18T512[40/80/16]0B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM Package Outline P(G)-TFBGA-84-51 60 Internet Data Sheet ...
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Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.1, 2007-05 03292006-YBYM-WG0Z HYB18T512[40/80/16]0B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM Package Outline P-TFBGA-84-1 61 Internet Data Sheet FIGURE 12 ...
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Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.1, 2007-05 03292006-YBYM-WG0Z HYB18T512[40/80/16]0B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM Package Outline P(G)-TFBGA-60-6 62 Internet Data Sheet FIGURE 13 ...
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... Internet Data Sheet HYB18T512[40/80/16]0B[C/F] TABLE 56 Examples for Nomenclature Fields — – –3.7 TABLE 57 DDR2 Memory Components Coding Constant SSTL_18 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit ×4 ×8 ×16 look up table First Second Third FBGA, lead-containing FBGA, lead-free ...
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List of Figures Chip Configuration for ×4 components, PG-TFBGA-60 (top view ...
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List of Tables Table 1 Performance Table for –25F and –2 ...
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... Clock-Jitter Specifications for –667 and –800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 54 ODT AC Characteristics and Operating Conditions for DDR2-533 and DDR2-400 . . . . . . . . . . . . . . . . . . . . . 59 Table 55 ODT AC Characteristics and Operating Conditions for DDR2-667 and DDR2-800 . . . . . . . . . . . . . . . . . . . . . 59 Table 56 Examples for Nomenclature Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 57 DDR2 Memory Components Rev. 1.1, 2007-05 03292006-YBYM-WG0Z HYB18T512[40/80/16]0B[C/F] 512-Mbit Double-Data-Rate-Two SDRAM 66 Internet Data Sheet ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Edition 2007-05 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or ...