HYB18T512800BF QIMONDA [Qimonda AG], HYB18T512800BF Datasheet
HYB18T512800BF
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HYB18T512800BF Summary of contents
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HYS72T64000HP–[25F/2.5/3/3S/3.7]–B HYS72T128000HP–[25F/2.5/3/3S/3.7]–B HYS72T128020HP–[25F/2.5/3/3S/3.7]–B HYS72T256220HP–[25F/2.5/3/3S/3.7]– ...
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HYS72T64000HP–[25F/2.5/3/3S/3.7]–B, HYS72T128000HP–[25F/2.5/3/3S/3.7]–B, HYS72T128020HP–[25F/2.5/3/3S/3.7]–B, HYS72T256220HP–[25F/2.5/3/3S/3.7]–B Revision History: 2007-03, Rev. 1.1 All Adapted internet edition All Updated for HYS72T[64/128/256]×××–3.7–B Product Types Previous Revision: 2006-12, Rev. 1.01 All Qimonda update Previous Revision: 2006-03, Rev. 1.0 We Listen to Your Comments Any information within ...
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... Features • 240-Pin PC2–6400, PC2–5300 and PC2–4200 DDR2 SDRAM memory modules. • One rank 64M ×72, 128M ×72, and two ranks 128M ×72, 256M ×72 module organization, and 512M ×8, 512M ×4 chip organization • ...
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... DIMMs are available as ECC modules in 64M × 72 (512 MB), 128M × GB), 256M x72 (2GB) organization and density, intended for mounting into 240-Pin connector sockets. The memory array is designed with 512-Mbit Double-Data- Rate-Two (DDR2) Synchronous DRAMs. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution ...
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... Product Type DRAM Components HYS72T64000HP HYB18T512800BF HYS72T128000HP HYB18T512400BF HYS72T128020HP HYB18T512800BF HYS72T256220HP HYB18T512400BF 1) Green Product 2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet. Rev. 1.1, 2007-03 03292006-EO3M-LEK7 HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B 240-Pin Registered DDR2 SDRAM ...
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Pin Configuration The pin configuration of the Registered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns Pin and Buffer Type are explained in Ball No. Name Pin Type Clock Signals ...
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Ball No. Name Pin Type 188 A0 I 183 182 180 179 A8 I 177 A10 ...
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Ball No. Name Pin Type Data Signals 3 DQ0 I/O 4 DQ1 I/O 9 DQ2 I/O 10 DQ3 I/O 122 DQ4 I/O 123 DQ5 I/O 128 DQ6 I/O 129 DQ7 I/O 12 DQ8 I/O 13 DQ9 I/O 21 DQ10 I/O ...
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Ball No. Name Pin Type 206 DQ39 I/O 89 DQ40 I/O 90 DQ41 I/O 95 DQ42 I/O 96 DQ43 I/O 208 DQ44 I/O 209 DQ45 I/O 214 DQ46 I/O 215 DQ47 I/O 98 DQ48 I/O 99 DQ49 I/O 107 DQ50 ...
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Ball No. Name Pin Type Data Strobe Bus 7 DQS0 I/O 6 DQS0 I/O 16 DQS1 I/O 15 DQS1 I/O 28 DQS2 I/O 27 DQS2 I/O 37 DQS3 I/O 36 DQS3 I/O 84 DQS4 I/O 83 DQS4 I/O 93 DQS5 ...
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Ball No. Name Pin Type Data Mask 125 DM0 I 134 DM1 I 146 DM2 I 155 DM3 I 202 DM4 I 211 DM5 I 223 DM6 I 232 DM7 I 164 DM8 I EEPROM 120 SCL I 119 SDA ...
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Ball No. Name Pin Type Other Pins 19, 102, 137, 138 220, 221 195 ODT0 I 77 ODT1 Abbreviation SSTL CMOS OD Abbreviation I O I/O AI PWR GND NU NC Rev. 1.1, 2007-03 03292006-EO3M-LEK7 ...
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Rev. 1.1, 2007-03 03292006-EO3M-LEK7 HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B 240-Pin Registered DDR2 SDRAM Pin Configuration for RDIMM (240 pins) 13 Internet Data Sheet FIGURE 1 ...
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Electrical Characteristics 3.1 Absolute Maximum Ratings Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Symbol Parameter V V Voltage on pin relative Voltage on pin relative to ...
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DC Characteristics Parameter Operating temperature (ambient) DRAM Case Temperature Storage Temperature Barometric Pressure (operating & storage) Operating Humidity (relative) 1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the ...
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Component AC Characteristics 3.3.1 Speed Grade Definitions All Speed grades faster than DDR2-DDR400B comply with DDR2-DDR400B timing specifications( Speed Grade Definition Tables: Table 12 Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ ...
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Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time 1) Timings are guaranteed with CK/CK differential Slew ...
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Timing Parameters Component AC Timing parameter: Table 15 Parameter DQ output access time from CAS to CAS command delay Average clock high pulse width Average clock period CKE minimum pulse width ( high and low pulse ...
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Parameter Read postamble Internal Read to Precharge command delay Write preamble Write postamble Write recovery time Internal write to read command delay Exit power down to read command Exit active power-down mode to read command (slow exit, lower power) Exit ...
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These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. crossing. That is, ...
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Parameter DQ output access time from CAS to CAS command delay Average clock high pulse width Average clock period CKE minimum pulse width ( high and low pulse width) Average clock low pulse width Auto-Precharge write recovery ...
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Parameter Write postamble Write recovery time Internal write to read command delay Exit power down to read command Exit active power-down mode to read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or ...
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Input waveform timing with differential data strobe enabled MR[bit10 referenced from the input signal crossing at the DS to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at ...
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Rev. 1.1, 2007-03 03292006-EO3M-LEK7 HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B 240-Pin Registered DDR2 SDRAM Method for calculating transitions and endpoint Differential input waveform timing - Differential input waveform timing - 24 Internet Data Sheet FIGURE 2 FIGURE and DS DS FIGURE 4 ...
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Parameter DQ output access time from CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks ...
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Parameter Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Active bank A to Active bank B ...
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The , and , parameters are referenced to a specific voltage level, which specify when the device output is no longer driving HZ RPST LZ RPRE begins ...
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ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400 Symbol Parameter / Condition t ODT turn-on delay AOND t ODT turn-on AON t ODT turn-on (Power-Down Modes) AONPD t ODT turn-off delay AOFD t ODT turn-off AOF t ODT ...
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I 3.4 Specifications and Conditions DD Parameter Operating Current One bank Active - Precharge CK.MIN valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current 1 I One bank Active - ...
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Parameter Self-Refresh Current CKE ≤ 0.2 V; external clock off, CK and Other control and address inputs are FLOATING, Data I bus inputs are FLOATING. current values are guaranteed up to DD6 All Bank Interleave Read ...
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Product Type Organization 512MB 1 Rank ×72 –25F Symbol Max. I 1190 DD0 I 1330 DD1 I 490 DD2P I 890 DD2N I 840 DD2Q I 780 DD3P( MRS = 0) I 510 DD3P( MRS = 1) I 970 DD3N ...
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Product Type Organization 512MB 1 Rank ×72 –2.5 Symbol Max. I 1150 DD0 I 1290 DD1 I 490 DD2P I 890 DD2N I 840 DD2Q I 780 DD3P( MRS = 0) I 510 DD3P( MRS = 1) I 970 DD3N ...
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Product Type Organization 512MB 1 Rank ×72 –3 Symbol Max. I 1060 DD0 I 1200 DD1 I 450 DD2P I 790 DD2N I 750 DD2Q I 680 DD3P( MRS = 0) I 470 DD3P( MRS = 1) I 840 DD3N ...
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Product Type Organization 512MB 1 Rank ×72 –3S Symbol Max. I 1020 DD0 I 1150 DD1 I 450 DD2P I 790 DD2N I 750 DD2Q I 680 DD3P( MRS = 0) I 470 DD3P( MRS = 1) I 840 DD3N ...
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Product Type Organization 512MB 1 Rank ×72 –3.7 Symbol Max. I 920 DD0 I 1010 DD1 I 390 DD2P I 670 DD2N I 650 DD2Q I 580 DD3P( MRS = 0) I 410 DD3P( MRS = 1) I 720 DD3N ...
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... Table 31 “SPD Codes for PC2–4200 - 444” on Page 53 Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank and Stacking Information 6 Data Width 7 Not used 8 ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 11 Error Correction Support (non-ECC, ECC) 12 Refresh Rate and Type 13 Primary SDRAM Width 14 Error Checking SDRAM Width 15 Not used 16 Burst Length Supported 17 Number of ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 36 [ns] WR.MIN t 37 [ns] WTR.MIN t 38 [ns] RTP.MIN 39 Analysis Characteristics and Extension RC RFC t 41 [ns] RC.MIN t 42 [ns] RFC.MIN ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description ∆ (DTREG) / Toggle Rate REG 62 SPD Revision 63 Checksum of Bytes 0-62 64 Manufacturer’s JEDEC ID Code (1) 65 Manufacturer’s JEDEC ID Code (2) 66 Manufacturer’s ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 86 Product Type, Char 14 87 Product Type, Char 15 88 Product Type, Char 16 89 Product Type, Char 17 90 Product Type, Char 18 91 Module Revision Code 92 ...
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... Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank and Stacking Information 6 Data Width 7 Not used 8 Interface Voltage Level (Byte 18) [ns] ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description (Byte 18) [ns] CK MAX t 24 SDRAM @ CL -1 [ns] AC MAX (Byte 18) [ns] CK MAX t ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description ∆ (DT0) 0 ∆ (DT2N, UDIMM) or ∆ ∆ (DT2P) 2P ∆ (DT3N) 3N ∆ (DT3P fast) ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 75 Product Type, Char 3 76 Product Type, Char 4 77 Product Type, Char 5 78 Product Type, Char 6 79 Product Type, Char 7 80 Product Type, Char 8 ...
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... Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank and Stacking Information 6 Data Width 7 Not used 8 Interface Voltage Level (Byte 18) [ns] ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 24 SDRAM @ CL -1 [ns] AC MAX (Byte 18) [ns] CK MAX t 26 SDRAM @ CL -2 [ns] AC MAX t 27 ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description ∆ (DT2N, UDIMM) or ∆ ∆ (DT2P) 2P ∆ (DT3N) 3N ∆ (DT3P fast) 3P.fast ∆ (DT3P ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 76 Product Type, Char 4 77 Product Type, Char 5 78 Product Type, Char 6 79 Product Type, Char 7 80 Product Type, Char 8 81 Product Type, Char 9 ...
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... Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank and Stacking Information 6 Data Width 7 Not used 8 Interface Voltage Level (Byte 18) [ns] ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description (Byte 18) [ns] CK MAX t 24 SDRAM @ CL -1 [ns] AC MAX (Byte 18) [ns] CK MAX t ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description ∆ (DT0) 0 ∆ T (DT2N, UDIMM) or ∆ ∆ (DT2P) 2P ∆ (DT3N) 3N ∆ (DT3P fast) ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 75 Product Type, Char 3 76 Product Type, Char 4 77 Product Type, Char 5 78 Product Type, Char 6 79 Product Type, Char 7 80 Product Type, Char 8 ...
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... Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank and Stacking Information 6 Data Width 7 Not used 8 Interface Voltage Level (Byte 18) [ns] ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description (Byte 18) [ns] CK MAX t 24 SDRAM @ CL -1 [ns] AC MAX (Byte 18) [ns] CK MAX t ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description ∆ (DT0) 0 ∆ (DT2N, UDIMM) or ∆ ∆ (DT2P) 2P ∆ (DT3N) 3N ∆ (DT3P fast) ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 75 Product Type, Char 3 76 Product Type, Char 4 77 Product Type, Char 5 78 Product Type, Char 6 79 Product Type, Char 7 80 Product Type, Char 8 ...
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Package Outlines Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.1, 2007-03 03292006-EO3M-LEK7 HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B 240-Pin Registered DDR2 SDRAM Package Outline Raw Card F L-DIM-240-11 57 Internet Data Sheet FIGURE 5 ...
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Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.1, 2007-03 03292006-EO3M-LEK7 HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B 240-Pin Registered DDR2 SDRAM Package Outline Raw Card H L-DIM-240-13 58 Internet Data Sheet FIGURE 6 ...
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Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.1, 2007-03 03292006-EO3M-LEK7 HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B 240-Pin Registered DDR2 SDRAM Package Outline Raw Card G L-DIM-240-12 59 Internet Data Sheet FIGURE 7 ...
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Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.1, 2007-03 03292006-EO3M-LEK7 HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B 240-Pin Registered DDR2 SDRAM Package Outline Raw Card J L-DIM-240-20 60 Internet Data Sheet FIGURE 8 ...
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Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.1, 2007-03 03292006-EO3M-LEK7 HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B 240-Pin Registered DDR2 SDRAM Package Outline Raw Card L L-DIM-240-48 61 Internet Data Sheet FIGURE 9 ...
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... Micro-DIMM HYS 64 DDR2 DRAM HYB 18 Field Description 1 Qimonda Module Prefix 2 Module Data Width [bit] 3 DRAM Technology 4 Memory Density per I/O [Mbit]; 1) Module Density 5 Raw Card Generation 6 Number of Module Ranks 7 Product Variations 8 Package, Lead-Free Status 9 Module Type Rev. 1.1, 2007-03 03292006-EO3M-LEK7 HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B field number ...
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... Field Description 10 Speed Grade 11 Die Revision 1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column “Coding”. Field Description 1 Qimonda Component Prefix ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Edition 2007-03 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or ...