HM628128 HITACHI [Hitachi Semiconductor], HM628128 Datasheet - Page 8

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HM628128

Manufacturer Part Number
HM628128
Description
1 M SRAM (128-kword x 8-bit)
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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11
HM628128D Series
Write Cycle
Parameter
Write cycle time
Address valid to end of write
Chip selection to end of write
Write pulse width
Address setup time
Write recovery time
Data to write time overlap
Data hold from write time
Output active from output in high-Z
Output disable to output in high-Z
WE to output in high-Z
Notes: 1. t
8
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, t
4. A write occurs during the overlap (t
5. t
6. t
7. t
8. During this period, I/O pins are in the output state; therefore, the input signals of the opposite
9. If the CS1 goes low or CS2 going high simultaneously with WE going low or after WE going low,
10. Dout is the same phase of the write data of this write cycle.
11. Dout is the read data of next address.
12. If CS1 is low and CS2 high during this period, I/O pins are in the output state. Therefore, the
13. In the write cycle with OE low fixed, t
and are not referred to output voltage levels.
device and from device to device.
at the later transition of CS1 going low, CS2 going high, or WE going low. A write ends at the
earlier transition of CS1 going high, CS2 going low, or WE going high. t
beginning of write to the end of write.
cycle.
phase to the outputs must not be applied.
the output remain in a high impedance state.
input signals of the opposite phase to the outputs must not be applied to them.
data bus contention. t
CHZ
CW
AS
WR
is measured from the address valid to the beginning of write.
, t
is measured from CS1 going low or CS2 going high to the end of write.
is measured from the earlier of WE or CS1 going high or CS2 going low to the end of write
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open circuit conditions
WP
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
WC
AW
CW
WP
AS
WR
DW
DH
OW
OHZ
WHZ
DW
min + t
WP
WP
HM628128D
-5
Min
55
50
50
40
0
0
20
0
5
0
0
) of a low CS1, a high CS2, and a low WE. A write begins
WHZ
must satisfy the following equation to avoid a problem of
max
Max
20
20
HZ
max is less than t
-7
Min
70
60
60
50
0
0
25
0
5
0
0
Max
25
25
LZ
min both for a given
WP
is measured from the
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
5
4, 13
6
7
2
1, 2, 8
1, 2, 8

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