E28F016XS20 INTEL [Intel Corporation], E28F016XS20 Datasheet
E28F016XS20
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E28F016XS20 Summary of contents
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... Combining very high read performance with the intrinsic nonvolatility of flash memory, the 28F016XS eliminates the traditional redundant memory paradigm of shadowing code from a slow nonvolatile storage source to a faster execution memory, such as DRAM, for improved system performance. The innovative capabilities of the 28F016XS enable the design of direct- execute code and mass storage data/file flash memory systems ...
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale ...
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... INTRODUCTION ............................................ 7 1.1 Product Overview ........................................ 7 2.0 DEVICE PINOUT........................................... 10 2.1 Lead Descriptions ...................................... 12 3.0 MEMORY MAPS ........................................... 14 3.1 Extended Status Register Memory Map..... 15 4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS............. 16 4.1 Bus Operations for Word-Wide Mode (BYTE )........................................... 16 IH 4.2 Bus Operations for Byte-Wide Mode (BYTE ........................................... 17 IL 4.3 28F008SA—Compatible Mode Command Bus Definitions.......................................... 18 4.4 28F016XS— ...
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... FLASH MEMORY REVISION HISTORY Number -001 Original Version Removed support of the following features: -002 All page buffer operations (read, write, programming, Upload Device Information) Command queuing Software Sleep and Abort Erase all Unlocked Blocks and Two-Byte Write RY/BY# Configuration as part of the Device Configuration command Changed definition of “ ...
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... REVISION HISTORY (Continued) Number Require all V Tolerences to be within 5% of Operational Voltage -004 Pushed to 200 µA from 50 Max PPES I Is Pushed to 10 µA from 5 Max CCD Updated t at 3.3V AVAV Updated t at 3.3V and 5.0V ELEH 28F016XS FLASH MEMORY Description 5 ...
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... FLASH MEMORY This page intentionally left blank 6 ...
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... Product Overview The 28F016XS is a high-performance, 16-Mbit (16,777,216-bit) block erasable nonvolatile random access memory organized as either 1 Mword Mbyte x 8, subdivided into even and odd banks. Address A makes the bank selection. The 1 28F016XS includes sixteen 128-Kbyte (131,072 byte) blocks or sixteen 64-Kword (65,536 word) blocks ...
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... In addition, the 28F016XS has a master Write Protect pin (WP#) which prevents any modifications to memory blocks whose lock-bits are set. Writing of memory data is performed in either byte or word increments, typically within 6 µs at 12. which is a 33% improvement over the PP 28F008SA ...
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... X Decoder Address Register X Decoder Y Decoder Figure 1. 28F016XS Block Diagram Architectural Evolution Includes Synchronous Pipelined Read Interface, SmartVoltage Technology, and Extended Status Registers 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY DQ 0-7 Output Input Input Buffer Buffer Buffer I/O Logic Data Register ID Register CSR ...
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... DEVICE PINOUT The 28F016XS is pinout compatible with the 28F016SA/SV 16-Mbit FlashFile memory com- ponents, providing a performance upgrade path to the 28F016XS. The 28F016XS 56-Lead TSOP and SSOP pinout configurations are shown in Figures 2 and 3. ...
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... Figure 3. 28F016XS 56-Lead SSOP Pinout Configuration Shows Compatibility with the 28F016SA/SV, Allowing for Easy Performance Upgrades from Existing 16-Mbit Designs 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY DA28F016XS 45 56-LEAD SSOP ...
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... FLASH MEMORY 2.1 Lead Descriptions Symbol Type A INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when device mode. This address is latched in x8 data programs and ignored in x16 mode (i.e., the A A INPUT BANK-SELECT ADDRESS: Selects an even or odd bank in a selected block. ...
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... ADV# INPUT ADDRESS VALID: Indicates that a valid address is present on the address inputs. ADV# low at the rising edge of CLK latches the address on the address inputs into the flash memory and initiates a read access to the even or odd bank depending on the state of A RY/BY# OPEN READY/BUSY: Indicates status of the internal WSM ...
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... Block 8 64-Kword Block 7 64-Kword Block 6 64-Kword Block 5 64-Kword Block 4 64-Kword Block 3 64-Kword Block 2 64-Kword Block 1 0 64-Kword Block 0532_03 Figure 5. 28F016XS Memory Map (Word-Wide Mode) A 20-1 FFFFF F0000 EFFFF E0000 DFFFF D0000 CFFFF C0000 BFFFF B0000 AFFFF A0000 9FFFF 90000 8FFFF ...
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... FLASH MEMORY x16 Mode RESERVED RESERVED GSR RESERVED BSR 15 RESERVED RESERVED . . . RESERVED RESERVED GSR RESERVED BSR 0 RESERVED RESERVED 0532_05 Figure 7. Extended Status Register Memory Map (Word-Wide Mode) 9053204.DOC A 20-1 FFFFFH F0003H F0002H F0001H F0000H 0FFFFH 00003H 00002H 00001H 00000H 0532_06 15 ...
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... FLASH MEMORY 4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS 4.1 Bus Operations for Word-Wide Mode (BYTE Mode Notes RP 0–1 Latch Read 1,9, Address Inhibit 1 Latching Read Address Read 1,2,7 Output 1,6,7 Disable Standby 1,6,7 ...
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... CE 0– 10. Addresses are latched on the rising edge of CLK in conjunction with ADV# low. Address selects the odd bank, in both byte-wide mode and word-wide mode device configurations. 1 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY ) IL OE# WE# ADV# CLK ...
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... FLASH MEMORY 4.3 28F008SA—Compatible Mode Command Bus Definitions Command Notes Read Array Intelligent Identifier 1 Read Compatible Status Register 2 Clear Status Register 3 Program Alternate Program Block Erase/Confirm Erase Suspend/Resume ADDRESS AA = Array Address BA = Block Address IA = Identifier Address PA = Program Address X = Don’t Care NOTES: 1 ...
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... DCCD = Device Configuration Code Data NOTES can be the GSR address or any BSR address. See Figures 5 and 6 for Extended Status Register memory maps. 2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the actual lock-bit status. ...
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... FLASH MEMORY 4.5 Compatible Status Register WSMS ESS CSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy CSR.6 = ERASE-SUSPEND STATUS 1 = Erase Suspended 0 = Erase In Progress/Completed CSR.5 = ERASE STATUS 1 = Error In Block Erasure 0 = Successful Block Erase CSR.4 = DATA WRITE STATUS 1 = Error in Data Program 0 = Data Program Successful CSR ...
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... GSR.5 = DEVICE OPERATION STATUS 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running GSR.4–0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the GSR. 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY ...
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... FLASH MEMORY 4.7 Block Status Register BS BLS BOS BSR.7 = BLOCK STATUS 1 = Ready 0 = Busy BSR.6 = BLOCK LOCK STATUS 1 = Block Unlocked for Program/Erase 0 = Block Locked for Program/Erase BSR.5 = BLOCK OPERATION STATUS 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running BSR STATUS Error Detect, Operation Abort ...
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... NOTE: 1. Default SFI Configuration after power-up or return from deep power-down mode via RP# low. 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY SFI1 SFI0 NOTES: Default SFI Configuration on power-up or return from deep power-down mode is 4, allowing ...
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... FLASH MEMORY 5.0 ELECTRICAL SPECIFICATIONS 5.1 Absolute Maximum Ratings* Temperature Under Bias ....................0°C to +80°C Storage Temperature ................... –65°C to +125° 3.3V ± 5% Systems CC Symbol Parameter T Operating Temperature, Commercial with Respect to GND Supply Voltage with Respect to GND Voltage on any Pin (except V ...
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... LOAD Outputs for Timing Specifications NOTE: 1. Sampled, not 100% tested. Guaranteed by design obtain iBIS models for the 28F016XS, please contact your local Intel/Distribution Sales Office. 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY Notes Typ Max Units Test Conditions ...
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... FLASH MEMORY 5.3 Transient Input/Output Reference Waveforms 2.4 2.0 INPUT 0.8 0.45 AC test inputs are driven at V (2.4 VTTL) for a Logic “1” and V OH (2.0 VTTL) and V (0.8 VTTL). Output timing ends Figure 8. Transient Input/Output Reference Waveform (V for Standard Testing Configuration 3.0 INPUT 1.5 0.0 AC test inputs are driven at 3.0V for a Logic “1” and 0.0V for a Logic “0.” Input timing begins, and output timing ends, at 1.5V. ...
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... I V Deep 1 CCD CC Power-Down Current Word/Byte 1,4,5 CCR CC Read Current Word/Byte 1,4, CCR CC 5,6 Read Current 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY Min Typ Max Units Test Conditions 1 µ GND µ OUT CC 70 130 µ ...
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... FLASH MEMORY 5.4 DC Characteristics (Continued 3.3V ± 5 0°C to +70° 3/5# = Pin Set High for 3.3V Operations Symbol Parameter Notes I V Program 1,6 CCW CC Current I V Block Erase 1,6 CCE CC Current I V Erase 1,2 CCES CC Suspend Current I V Standby/Read 1 PPS PP I Current PPR I V Deep Power- ...
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... PPLK PPH1 4. Automatic Power Savings (APS) reduces I CCR 5. CMOS Inputs are either V ± 0.2V or GND ± 0.2V. TTL Inputs are either Sampled, but not 100% tested. Guaranteed by design. 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY Min Typ Max Units Test Conditions 0.0 1.5 V 4.5 5.0 5 ...
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... FLASH MEMORY 5.5 DC Characteristics V = 5.0V ± 5 0°C to +70° 3/5# = Pin Set Low for 5.0V Operations Parameter Notes Symbol I Input Load Current Output Leakage 1 LO Current I V Standby 1,5 CC CCS Current I V Deep Power CCD Down Current Read Current 1,4,5 CCR ...
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... Input High Voltage Output Low 6 OL Voltage V 1 Output High 6 OH Voltage 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY Min Typ Max Units Test Conditions 12.0V ± Program in Progress 5.0V ± 10% PP Program in Progress ...
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... FLASH MEMORY 5.5 DC Characteristics (Continued 5.0V ± 5 0°C to +70° 3/5# = Pin Set Low for 5.0V Operations Parameter Notes Symbol V V 3,6 PPLK PP Program/Erase Lock Voltage V V during PPH1 PP Program/Erase Operations V V during PPH2 PP Program/Erase Operations V V LKO CC Program/Erase Lock Voltage NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at V currents are valid for all product versions (package and speeds) and are specified for a CMOS rise/fall time (10% to 90%) of < ...
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... W WE# (Write Enable) P RP# (Deep Power-Down Pin) R RY/BY# (Ready Busy) V ADV# (Address Valid) Y 3/5# Pin 4.5V Minimum 3.0V Minimum CC 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY Pin States H High L Low V Valid X Driven, but Not Necessarily Valid Z High Impedance L Latched 9053204.DOC 33 ...
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... FLASH MEMORY 5.7 AC Characteristics—Read Only Operations V = 3.3V ± 5 0°C to +70° (3) Versions Symbol Parameter f CLK Frequency CLK t CLK Period CLK t CLK High Time CH t CLK Low Time CL t CLK Rise Time CLCH t CLK Fall Time CHCL Setup to CLK ...
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... See the high speed AC Input/Output Reference Waveforms. 5. See the standard AC Input/Output Reference Waveforms defined as the latter going low, or the first 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY (1) (Continued) (4) 28F016XS-15 28F016XS-20 Notes Min Max Min ...
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... FLASH MEMORY CLCH Figure 10. CLK Waveform CLK ADDR t CHAX CLK Periods t AVCH ADV# t VLCH t CHVH CEx# t ELCH t ELQX OE# t GLCH Even t GLQX DATA NOTE: 1. The 28F016XS can sustain an optimized burst access throughout the 28F016XS array assuming alternating bank accesses ...
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... The 28F016XS can sustain an optimized burst access throughout the 28F016XS array assuming alternating bank accesses; the length of the burst access is dictated by the control CPU or bus architecture. Figure 12. Read Timing Waveform (SFI Configuration = 2, Alternate-Bank Accesses) 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY t EHQZ t OH Odd Even ...
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... FLASH MEMORY CLK ADDR t CHAX CLK Periods t AVCH ADV# t VLCH t CHVH CEx# t ELCH t ELQX OE# t GLCH Even t GLQX DATA NOTES: 1. The 28F016XS can sustain an optimized burst access throughout the 28F016XS array assuming alternating bank accesses; the length of the burst access is dictated by the control CPU or bus architecture. ...
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... The 28F016XS can sustain an optimized burst access throughout the 28F016XS array assuming alternating bank accesses; the length of the burst access is dictated by the control CPU or bus architecture. Figure 14. Read Timing Waveform (SFI Configuration = 4, Alternating Bank Accesses) 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY t EHQZ Odd Even Odd t ...
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... FLASH MEMORY 5.8 AC Characteristics for WE#—Controlled Write Operations V = 3.3V ± 5 0°C to +70° Versions Symbol Parameter t Write Cycle Time AVAV t 1,2 V Setup to WE# Going VPWH PP High t RP# Setup Going PHEL X Low Setup to WE# Going ELWL X Low t Address Setup to WE# ...
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... QVVL PP Register (CSR, GSR, BSR) Data and RY/BY# High t 1 Duration of Program WHQV Operation t 2 Duration of Block Erase WHQV Operation 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY (1) (Continued) 28F016XS-15 28F016XS-20 Notes Min Typ Max Min Typ 100 100 3,7 300 300 ...
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... FLASH MEMORY NOTES: 1. Read timings during program and erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, but not 100% tested. Guaranteed by design. 4. Program/erase durations are measured to valid Status Register (CSR) Data. ...
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... Data program/erase cycles are asynchronous; CLK and ADV# are ignored voltage during data program/erase operations valid at both 12.0V and 5. voltage equal to or below V provides complete flash memory array protection. PP PPLK Figure 15. AC Waveforms for WE#—Command Write Operations, Illustrating a Two Command Write Sequence Followed by an Extended Status Register Read 4/15/97 9:41 AM ...
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... FLASH MEMORY 5.9 AC Characteristics for 3.3V ± 5 0°C to +70° Versions Symbol Parameter t Write Cycle Time AVAV t 1,2 V Setup Going VPEH PP X High t RP# Setup to WE# Going PHWL Low t WE# Setup Going WLEL X Low t Address Setup to CE ...
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... QVVL PP Register (CSR, GSR, BSR) Data and RY/BY# High t 1 Duration of Program EHQV Operation t 2 Duration of Block Erase EHQV Operation 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY #—Controlled Write Operations X 28F016XS-15 28F016XS-20 Notes Min Typ Max Min 60 60 3,7 100 100 3 300 ...
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... FLASH MEMORY NOTES: 1. Read timings during write and erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, but not 100% tested. Guaranteed by design. 4. Program/erase durations are measured to valid Status Register (CSR) Data. ...
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... Data program/erase cycles are asynchronous; CLK and ADV# are ignored voltage during data program/erase operations valid at both 12.0V and 5. voltage equal to or below V provides complete flash memory array protection. PP PPLK Figure 16. AC Waveforms for CE Illustrating a Two Command Write Sequence Followed by an Extended Status Register Read 4/15/97 9:41 AM ...
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... FLASH MEMORY 5.10 Power-Up and Reset Timings V POWER-UP CC RP# t YHPH (P) 3/5# (Y) 3. (3V,5V) NOTE: For read timings following reset see Section 5.7. Figure 17 Symbol Parameter t RP# Low to 3/5# Low (High) PLYL t PLYH t 3/5# Low (High) to RP# High YLPH t YHPH t RP# Low 4.5V (Minimum) PL5V ...
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... WHRH t 2 Block Program Time 2,5 WHRH t 3 Block Program Time 2,5 WHRH Block Erase Time 2 Erase Suspend Latency Time to Read 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY (3,4) (1) Min Typ Max Units Test Conditions TBD 29 TBD µs TBD 35 TBD µs TBD 3.8 TBD ...
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... FLASH MEMORY 5.11 Erase and Program Performance V = 5.0V ± 5 5.0V ± 5 0°C to +70° Symbol Parameter Notes t 1A Byte Program Time 2,5 WHRH t 1B Word Program Time 2,5 WHRH t 2 Block Program Time 2,5 WHRH t 3 Block Program Time 2,5 WHRH Block Erase Time ...
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... Symbol Minimum 0.050 A 2 0.965 b 0.100 c 0.115 D 1 18.20 E 13. 19.80 L 0.500 0.150 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY Millimeters Nominal Maximum 1.20 0.995 1.025 0.150 0.200 0.125 0.135 18.40 18.60 14.00 14.20 0.50 20.00 20.20 0.600 0.700 0.100 0.250 0.350 9053204.DOC 048928.eps Notes ...
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... FLASH MEMORY Figure 19. Mechanical Specifications of the 28F016SV 56-Lead SSOP Type I Package Family: Shrink Small Out-Line Package Symbol Minimum A A1 0.47 A2 1.18 B 0.25 C 0.13 D 23.40 E 13. 15. 0. 2° b 3° R1 0. Detail See Detail A ...
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... Package DA = SSOP E = TSOP Device Density 016 = 16 Mbit Product Family X = Fast Flash Option Order Code V 1.5V I/O Levels 1 E28F016XS15 2 E28F016XS20 3 DA28F016XS15 4 DA28F016XS20 NOTE: 1. See Section 5.3 for Transient Input/Output Reference Waveforms. 4/15/97 9:41 AM INTEL CONFIDENTIAL (until publication date) 28F016XS FLASH MEMORY APPENDIX Period of Maximum CLK ...
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... AP-398 Designing with the 28F016XS 292146 AP-600 Performance Benefits and Power/Energy Savings of 28F016XS- Based System Designs 292163 AP-610 Flash Memory In-System Code and Data Update Techniques AB-62 Compiled Code Optimizations for Flash Memories 292165 297500 Interfacing the 28F016XS to the i960 297504 Interfacing the 28F016XS to the Intel486™ ...