XCF16PVO48C XILINX [Xilinx, Inc], XCF16PVO48C Datasheet
XCF16PVO48C
Available stocks
Related parts for XCF16PVO48C
XCF16PVO48C Summary of contents
Page 1
R DS123 (v2.11.1) March 30, 2007 Features • In-System Programmable PROMs for Configuration of Xilinx FPGAs • Low-Power Advanced CMOS NOR FLASH Process • Endurance of 20,000 Program/Erase Cycles • Operation over Full Industrial Temperature Range (–40°C to +85°C) • ...
Page 2
R CLK TCK Control TMS and JTAG TDI Interface TDO CF Figure 1: XCFxxS Platform Flash PROM Block Diagram FI CLK CE OSC Control TCK and TMS TDI JTAG TDO Interface CF Figure 2: XCFxxP Platform Flash PROM Block Diagram ...
Page 3
R The Platform Flash PROMs are compatible with all of the existing FPGA device families. A reference list of Xilinx FPGAs and the respective compatible Platform Flash PROMs is given in given in Table 3, page 4. Table 2: Xilinx ...
Page 4
R Table 2: Xilinx FPGAs and Compatible Platform Flash PROMs (Continued) Configuration FPGA Platform Flash PROM Bitstream Virtex FPGAs XCV50 559,200 XCV100 781,216 XCV150 1,040,096 XCV200 1,335,840 XCV300 1,751,808 XCV400 2,546,048 XCV600 3,607,968 XCV800 4,715,616 XCV1000 6,127,744 Spartan™-3A FPGAs XC3S50A ...
Page 5
R Programming The Platform Flash PROM is a reprogrammable NOR flash device (refer "Quality and Reliability Characteristics," page 27 for the program/erase specifications). Reprogramming requires an erase followed by a program operation. A verify operation is recommended after the program ...
Page 6
R Design Security The Xilinx in-system programmable Platform Flash PROM devices incorporate advanced data security features to fully protect the FPGA programming data against unauthorized reading via JTAG. The XCFxxP PROMs can also be programmed to prevent inadvertent writing via ...
Page 7
R IEEE 1149.1 Boundary-Scan (JTAG) The Platform Flash PROM family is compatible with the IEEE 1149.1 boundary-scan standard and the IEEE 1532 in-system configuration standard. A Test Access Port (TAP) and registers are provided to support all required boundary scan ...
Page 8
R Table 7: XCFxxS Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence IR[7:5] TDI → Reserved Table 8: XCFxxP Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence IR[15:9] IR[8:7] TDI ...
Page 9
R Platform Flash PROM TAP Characteristics The Platform Flash PROM family performs both in-system programming and IEEE 1149.1 boundary-scan (JTAG) testing via a single 4-wire Test Access Port (TAP). This simplifies system designs and allows standard Automatic Test Equipment to ...
Page 10
R Additional Features for the XCFxxP Internal Oscillator The 8/16/32 Mbit XCFxxP Platform Flash PROMs include an optional internal oscillator which can be used to drive the CLKOUT and DATA pins on FPGA configuration interface. The internal oscillator can be ...
Page 11
R Larger design revisions can be split over several cascaded PROMs. For example, two 32-Mbit PROMs can store up to four separate design revisions: one 64-Mbit design revision, two 32-Mbit design revisions, three 16-Mbit design revisions, four 16-Mbit design revisions, ...
Page 12
R PROM to FPGA Configuration Mode and Connections Summary The FPGA's I/O, logical functions, and internal interconnections are established by the configuration data contained in the FPGA’s bitstream. The bitstream is loaded into the FPGA either automatically upon power up, ...
Page 13
R Serial Daisy Chain Multiple FPGAs can be daisy-chained for serial configuration from a single source. After a particular FPGA has been configured, the data for the next device is routed internally to the FPGA’s DOUT pin. Typically the data ...
Page 14
R CCLK. If BUSY is asserted (High) by the FPGA, the configuration data must be held until BUSY goes Low. An external data source or external pull-down resistors must be used to enable the FPGA's active Low Chip Select (CS ...
Page 15
R Initiating FPGA Configuration The options for initiating FPGA configuration via the Platform Flash PROM include: • Automatic configuration on power up • Applying an external PROG_B (or PROGRAM) pulse • Applying the JTAG CONFIG instruction Following the FPGA’s power-on ...
Page 16
R Configuration PROM to FPGA Device Interface Connection Diagrams CCJ CCO CCINT V CCINT (2) V CCO (2) V CCJ Platform Flash PROM OE/RESET TDI TDI TMS TMS TCK TCK TDO GND Notes: 1 For Mode pin ...
Page 17
R (3) External Oscillator CCJ CCO CCINT V CCINT (2) V CCO (2) V CCJ Platform Flash PROM OE/RESET TDI TDI TMS TMS TCK TCK TDO GND Notes: 1 For Mode pin connections and DONE pin pull-up ...
Page 18
CCJ CCO CCINT CCJ V D0 CCINT (2) V CCO (2) V CCJ Platform Flash PROM Cascaded CLK PROM CE (PROM 1) CEO OE/RESET (3) TDI TDI CF TMS TMS TCK TCK TDO TDO GND ...
Page 19
CCJ CCO CCINT V CCINT (2) V CCO (2) V CCJ XCFxxP Platform Flash PROM OE/RESET TDI TDI TMS TMS BUSY TCK TCK TDO GND Notes: 1 For Mode pin connections and DONE pin pull-up value, ...
Page 20
R (5) External Oscillator CCJ CCO CCINT V CCINT (2) V CCO (2) V CCJ XCFxxP Platform Flash PROM OE/RESET TDI TDI TMS TMS BUSY TCK TCK TDO GND Notes: 1 For Mode pin connections and DONE ...
Page 21
CCJ CCO CCINT CCJ V D[0:7] CCINT CCO (2) V CCJ (2) V XCFxxP Platform Flash PROM Cascaded CLK PROM CE (PROM 1) CEO OE/RESET (5) TDI TDI CF (4) TMS TMS BUSY TCK ...
Page 22
CCJ CCO CCINT CCJ (3) External Oscillator V D0 CCINT CCO (2) V CCJ (2) V XCFxxP Platform Flash PROM (3) Cascaded CLK PROM CE (PROM 1) CEO OE/RESET (4) TDI TDI CF TMS TMS ...
Page 23
CCJ CCO CCINT CCJ (5) External Oscillator V D[0:7] CCINT CCO (2) V CCJ (2) V XCFxxP Platform Flash PROM Cascaded (5) CLK PROM CE (PROM 1) CEO OE/RESET (6) TDI TDI CF (4) ...
Page 24
R Reset and Power-On Reset Activation At power up, the device requires the V monotonically rise to the nominal operating voltage within the specified V rise time. If the power supply cannot CCINT meet this requirement, then the device might ...
Page 25
R Standby Mode The PROM enters a low-power standby mode whenever CE is deasserted (High). In standby mode, the address counter is reset, CEO is driven High, and the remaining outputs are placed in a high-impedance state regardless of the ...
Page 26
R DC Electrical Characteristics Absolute Maximum Ratings Symbol Description V Internal supply voltage relative to GND CCINT V I/O supply voltage relative to GND CCO V JTAG I/O supply voltage relative to GND CCJ V Input voltage with respect to ...
Page 27
R Recommended Operating Conditions Symbol Description V Internal voltage supply CCINT V 3.3V Operation CCO Supply voltage 2.5V Operation for output 1.8V Operation drivers 1.5V Operation V 3.3V Operation Supply voltage CCJ for JTAG output 2.5V Operation drivers V 3.3V ...
Page 28
R DC Characteristics Over Operating Conditions Symbol Description High-level output voltage for 3.3V outputs High-level output voltage for 2.5V outputs V OH High-level output voltage for 1.8V outputs High-level output voltage for 1.5V outputs Low-level output voltage for 3.3V outputs ...
Page 29
R AC Electrical Characteristics AC Characteristics Over Operating Conditions XCFxxS and XCFxxP PROM as Configuration Slave with CLK Input Pin as Clock Source T SCE CE OE/RESET CLK BUSY T OE (optional DATA HCF CF ...
Page 30
R Symbol Description (6) Clock period (serial mode) when V (6) Clock period (serial mode) when V T CYC (6) Clock period (parallel mode) when V (6) Clock period (parallel mode) when V (3) CLK Low time when V T ...
Page 31
R XCFxxP PROM as Configuration Master with CLK Input Pin as Clock Source CE OE/RESET CLK CLKOUT T CECC T OECC BUSY T OE (optional DATA CFCC T HCF CF EN_EXT_SEL T T SXT HXT ...
Page 32
R Symbol (7) Clock period (serial mode) when V (7) Clock period (serial mode) when V T CYCO (7) Clock period (parallel mode) when V (7) Clock period (parallel mode) when V (3) CLK Low time when ...
Page 33
R Symbol EN_EXT_SEL hold time from CF, CE, or OE/RESET when V T HXT EN_EXT_SEL hold time from CF, CE, or OE/RESET when V REV_SEL setup time to CF, CE, or OE/RESET when V T SRV REV_SEL setup time to ...
Page 34
R XCFxxP PROM as Configuration Master with Internal Oscillator as Clock Source CE OE/RESET CLKOUT T CEC T OEC BUSY T OE (optional DATA CFC T HCF CF EN_EXT_SEL T T SXT HXT T T ...
Page 35
R Symbol BUSY setup time to CLKOUT when BUSY setup time to CLKOUT when V BUSY hold time to CLKOUT when BUSY hold time to CLKOUT when V ( CLKOUT delay when ...
Page 36
R AC Characteristics Over Operating Conditions When Cascading OE/RESET CE CLK CLKOUT (optional) DATA CEO Symbol Description CLK to output float delay when V = 2.5V or 3.3V T CCO CDF CLK to output float delay (3,5) CLK to CEO ...
Page 37
R Pinouts and Pin Descriptions The XCFxxS Platform Flash PROM is available in the VO20 and VOG20 packages. The XCFxxP Platform Flash PROM is available in the VO48, VOG48, FS48, and FSG48 packages. For package drawings, specifications, and additional information, ...
Page 38
R Table 13: XCFxxS Pin Names and Descriptions (Continued) Boundary Boundary Scan Pin Name Scan Order Function VCCO – VCCJ – GND – DNC – XCFxxS VO20/VOG20 Pinout Diagram (DNC) 3 CLK 4 TDI VO20/VOG20 5 TMS ...
Page 39
R XCFxxP Pinouts and Pin Descriptions VXCFxxP O48/VOG48 and FS48/FSG48 Pin Names and Descriptions Table 14 provides a list of the pin names and descriptions for the XCFxxP 48-pin VO48/VOG48 and 48-pin FS48/FSG48 packages. Table 14: XCFxxP Pin Names and ...
Page 40
R Table 14: XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48) (Continued) Boundary Boundary Pin Name Scan Scan Order Function 06 Data Out CEO 05 Output Enable EN_EXT_SEL 31 Data In REV_SEL0 30 Data In REV_SEL1 29 Data In BUSY ...
Page 41
R Table 14: XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48) (Continued) Boundary Boundary Pin Name Scan Scan Order Function VCCO – VCCJ – GND – DNC – XCFxxP VO48/VOG48 Pinout Diagram DNC 1 GND 2 DNC 3 VCCINT 4 ...
Page 42
R XCFxxP FS48/FSG48 Pin Names Table 15: XCFxxP Pin Names (FS48/FSG48) Pin Pin Pin Name Number Number A1 GND E1 A2 GND E2 A3 OE/RESET E3 A4 DNC VCCINT F1 B2 VCCO ...
Page 43
R Ordering Information Device Number XCF01S Package Type XCF02S VO20 = 20-pin TSSOP Package XCF04S VOG20 = 20-pin TSSOP Package, Pb-free Device Number XCF08P Package Type XCF16P VO48 = 48-pin TSOP Package XCF32P VOG48 = 48-pin TSOP Package, Pb-free FS48 ...
Page 44
R Revision History The following table shows the revision history for this document. Date Version 04/29/03 1.0 Xilinx Initial Release. 06/03/03 1.1 Made edits to all pages. 11/05/03 2.0 Major revision. 11/18/03 2.1 Pinout corrections as follows: • • • ...
Page 45
R • Added Pb-free package options VOG20, FSG48, and VOG48. 07/20/04 2.4 • • Section • • 10/18/04 2.5 • • • Table • Table • Table • Table • Added Virtex-4 LX/FX/SX configuration data to 03/14/05 2.6 • Corrected ...
Page 46
R • Update to the first paragraph of 12/29/05 2.8 • Added JTAG cautionary note to • Corrected logic values for Erase/Program (ER/PROG) Status field, IR[4], listed under • Sections • Notes for • Enhanced description under section • Enhanced ...