PSD4235G2-12UIT STMICROELECTRONICS [STMicroelectronics], PSD4235G2-12UIT Datasheet
PSD4235G2-12UIT
Related parts for PSD4235G2-12UIT
PSD4235G2-12UIT Summary of contents
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... Built-in JTAG compliant serial port allows full-chip In-System Programmability – Efficient manufacturing allow easy product testing and programming – Use low cost FlashLINK cable with PC February 2009 PSD4235G2V for 16-bit MCUs (3.3 V supply) LQFP80 (U) 80-lead, Thin, Quad, Flat ■ Page register – ...
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... Direction registers - ports 5.4 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.5 Drive registers - Ports 5.6 Drive registers - Ports C and 2/124 First time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Inventory build-up of pre-programmed devices . . . . . . . . . . . . . . . . . . . 12 Expensive sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Simultaneous READ and WRITE to Flash memory . . . . . . . . . . . . . . . . 13 Complex memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Separate Program and Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PSD4235G2V ...
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... PSD4235G2V 5.7 Enable-Out registers - Ports 5.8 Input macrocells registers- ports 5.9 Output macrocells A/B registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.10 Mask macrocells A/B registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.11 Flash Memory Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.12 Flash Boot Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.13 JTAG Enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.14 Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.15 PMMR0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.16 PMMR2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.17 VM register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.18 Memory_ID0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.19 Memory_ID1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 Detailed operation ...
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... Separate space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.4 Combined space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.5 80C51XA memory map example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13 Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 14 Memory ID registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 15 PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 16 Decode PLD (DPLD Complex PLD (CPLD 17.1 Output macrocell (OMC 17.2 Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 17.3 Loading and Reading the output macrocells (OMC 4/124 PSD4235G2V ...
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... PSD4235G2V 17.4 The OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 17.5 The output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 17.6 Input macrocells (IMC 17.7 External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 18 MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 18.1 PSD interface to a multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 18.2 PSD interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . 66 18.3 Data Byte Enable reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 18.4 MCU bus interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 18.5 80C196 and 80C186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18 ...
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... I/O pin, register and PLD status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . 94 21.4 Reset of Flash Memory Erase and Program cycles . . . . . . . . . . . . . . . . . 94 22 Programming in-circuit using the JTAG serial interface . . . . . . . . . . . 96 22.1 Standard JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 22.2 JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 22.3 Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 23 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 24 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 25 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6/124 PSD4235G2V ...
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... PSD4235G2V 26 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 27 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Appendix A Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Contents 7/124 ...
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... Port Pin Direction Control, output Enable P.T. not defined Table 43. Port Pin Direction Control, output Enable P.T. defined Table 44. Port direction assignment example Table 45. Drive register pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 46. Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 47. Effect of Power-down mode on ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 48. PSD timing and standby current during Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . 91 8/124 PSD4235G2V ...
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... Table 72. ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 73. LQFP80 - 80-lead plastic thin, quad, flat package mechanical data 119 Table 74. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 75. PSD4235G2V LQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 76. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 = 3.0 V (with Turbo mode on 102 CC = 3.0 V (with Turbo mode off 103 CC List of tables ...
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... Asynchronous clock mode timing (product term clock 110 Figure 42. Input macrocell timing (product term clock 110 Figure 43. Peripheral I/O write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 44. READ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 45. WRITE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 46. Peripheral I/O read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 47. Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Figure 48. ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10/124 PSD4235G2V ...
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... PSD4235G2V Figure 49. LQFP80 - 80-lead plastic thin, quad, flat package outline . . . . . . . . . . . . . . . . . . . . . . . . 119 List of figures 11/124 ...
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... Two independent Flash memory arrays are included so that the MCU can execute code from one while erasing and programming the other. Robust product firmware updates in the filed are possible over any communication channel (CAN, Ethernet, UART, J1850, etc) using this unique architecture. Designers are relieved of these problems: 12/124 PSD4235G2V ...
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... PSD4235G2V 1.2.1 Simultaneous READ and WRITE to Flash memory How can the MCU program the same memory from which it executing code? It cannot. The PSD allows the MCU to operate the two Flash memory blocks concurrently, reading code from one while erasing and programming the other during IAP. ...
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... Pin names PA0-PA7 PB0-PB7 PC0-PC7 PD0-PD3 PE0-PE7 PF0-PF7 PG0-PG7 AD0-AD15 CNTL0-CNTL2 RESET 14/124 CNTL0- CNTL2 PSD4xxxGx 16 AD0-AD15 RESET V SS Pin Port-A Port-B Port-C Port-D Port-E Port-F Port-G Address/Data Control Reset PSD4235G2V 8 PA0-PA7 8 PB0-PB7 8 PC0-PC7 4 PD0-PD3 8 PE0-PE7 8 PF0-PF7 8 PG0-PG7 AI04916 Description ...
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... PSD4235G2V Table 1. Pin names (continued Figure 2. LQFP connections PD2 1 PD3 2 AD0 3 AD1 4 AD2 5 AD3 6 AD4 7 GND AD5 10 AD6 11 AD7 12 AD8 13 AD9 14 AD10 15 AD11 16 AD12 17 AD13 18 AD14 19 AD15 20 Pin Supply voltage Ground Description Description 60 CNTL1 59 CNTL0 58 PA7 57 PA6 ...
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... Description Figure 3. PSD block diagram 1. Additional address lines can be brought in to the device via Port 16/124 PSD4235G2V AI04990b ...
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... PSD4235G2V 2 PSD architectural overview PSD devices contain several major functional blocks. PSD device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable. 2.1 Memory Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed discussion can be found in The 4 Mbit primary Flash memory is the main memory of the PSD ...
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... The secondary Flash memory can be programmed the same way by executing out of the primary Flash memory. different functional blocks of the PSD. 18/124 Table 3 Name Inputs 82 82 TMS TCK TDI TDO TSTAT TERR Table 4 indicates which programming methods can program PSD4235G2V indicates the JTAG pin assignments. Outputs Product Terms 150 JTAG signal ...
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... PSD4235G2V 2.8 Page register The 8-bit Page register expands the address range of the MCU 256 times. The paged address can be used as part of the address space to access external memory and peripherals, or internal memory and I/O. The Page register can also be used to change the address mapping of the Flash memory blocks into different memory spaces for IAP ...
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... PSDsoft Express directly supports two low cost device programmers form ST: PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local distributor/representative, or directly from our web site using a credit card. The PSD is also supported by third party device programmers. See our web site for the current list. 20/124 PSD4235G2V Figure 4. ...
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... PSD4235G2V Figure 4. PSDsoft Express development tool Choose MCU and PSD Automatically configures MCU bus interface and other Define PSD Pin and Point and click definition of PSD pin functions, internal nodes, and MCU system memory map Define General Purpose Point and click definition of combin- atorial and registered logic in CPLD ...
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... Read only - Primary Flash Sector C0 Protection Read only - PSD Security and C2 secondary Flash memory Sector Protection C7 Enables JTAG Port B0 Power Management register 0 B4 Power Management register 2 E0 Page register Places PSD memory areas in E2 Program and/or Data space on an individual basis. PSD4235G2V ...
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... PSD4235G2V Table 5. Register address offset (continued) Port Port Port Register name A B Memory_ID0 Memory_ID1 1. Other registers that are not part of the I/O ports. PSD register description and address offsets Port Port Port Port (1) Other Description Read only - SRAM and primary ...
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... Port pin 4 Port pin 3 Bit 5 Bit 4 Bit 3 Port pin 5 Port pin 4 Port pin 3 Bit 5 Bit 4 Bit 3 Port pin 5 Port pin 4 Port pin 3 PSD4235G2V Bit 2 Bit 1 Bit 0 Port pin 2 Port pin 1 Port pin 0 Bit 2 Bit 1 Bit 0 Port pin 2 Port pin 1 Port pin 0 Bit 2 ...
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... PSD4235G2V 5.5 Drive registers - Ports Table 10. Drive registers - Ports Bit 7 Bit 6 Port pin 7 Port pin 6 Port pin <i>: 0: Port pin <i> is configured for CMOS output driver (default). 1: Port pin <i> is configured for Open Drain output driver. 5.6 Drive registers - Ports C and F Table 11. ...
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... Bit 4 Bit 3 Mcellb 5 Mcellb 4 Mcellb 3 Bit 5 Bit 4 Bit 3 Mcella 5 Mcella 4 Mcella 3 Bit 5 Bit 4 Bit 3 Mcellb 5 Mcellb 4 Mcellb 3 Bit 5 Bit 4 Bit 3 PSD4235G2V Bit 2 Bit 1 Bit 0 Mcella 2 Mcella 1 Mcella 0 Bit 2 Bit 1 Bit 0 Mcellb 2 Mcellb 1 Mcellb 0 Bit 2 Bit 1 Bit 0 Mcella 2 Mcella 1 Mcella 0 Bit 2 Bit 1 ...
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... PSD4235G2V 5.12 Flash Boot Protection register Table 19. Flash Boot Protection register Bit 7 Bit 6 Security_ not used Bit Sec<i>_Prot: 1: Secondary Flash memory Sector <i> is write protected. 0: Secondary Flash memory Sector <i> is not write protected. Security_Bit: 0: Security bit in device has not been set. 1: Security bit in device has been set. ...
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... ALE input to the PLD AND array is disconnected, saving power. 28/124 Bit 5 Bit 4 Bit 3 PLD PLD Array PLD Array CNTL2 CNTL1 Array ALE Table 33 for the signals that are blocked on pins CNTL0-CNTL2. PSD4235G2V Bit 2 Bit 1 Bit 0 not used PLD PLD Array CNTL0 (set to ’0’) Array Addr ...
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... PSD4235G2V PLD Array WRH 0: WRH/DBE input to the PLD AND array is connected. 1: WRH/DBE input to the PLD AND array is disconnected, saving power. 5.17 VM register Table 24. VM register Bit 7 Bit 6 not used Peripheral mode (set to ’0’) On reset, bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft Express ...
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... Secondary NVM size is 256 Kbit 3h = Secondary NVM size is 512 Kbit B_type[1: Secondary NVM is Flash memory 1h = Secondary NVM is EEPROM 30/124 Bit 5 Bit 4 Bit 3 S_size 1 S_size 0 F_size 3 Bit 5 Bit 4 Bit 3 B_type 1 B_type 0 B_size 3 PSD4235G2V Bit 2 Bit 1 Bit 0 F_size 2 F_size 1 F_size 0 Bit 2 Bit 1 Bit 0 B_size 2 B_size 1 B_size 0 ...
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... PSD4235G2V 6 Detailed operation As shown in Figure ● Memory blocks ● PLD blocks ● MCU bus Interface ● I/O ports ● Power management unit (PMU) ● JTAG-ISP interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. ...
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... Program instruction, then test the status of the Programming event. This status test is achieved by a READ operation or polling Ready/Busy (PE4). Flash memory can also be read by using special instructions to retrieve particular Flash device information (sector protect status and ID). 32/124 PSD4235G2V Section 15: ...
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... PSD4235G2V (1)(2)(3) Table 28. Instructions FS0-FS7 or (4) Instruction CSBOOT0- CSBOOT3 (6) READ 1 (7) Read Main Flash ID 1 Read Sector (7)(8) Protection 1 (9) Program a Flash 1 (9) Word Flash Sector 1 (10)(9) Erase (9) Flash Bulk Erase 1 Suspend Sector 1 (11) Erase Resume Sector 1 (12) Erase (7) Reset 1 Unlock Bypass 1 Unlock Bypass ...
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... The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode. 13. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction. 14. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass mode. 34/124 PSD4235G2V ...
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... PSD4235G2V 7 Instructions An instruction consists of a sequence of specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the timeout period. Some instructions are structured to include READ operations after the initial WRITE operations ...
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... Erase or Program instruction is being executed by the embedded algorithm. See Section 8: Programming Flash 36/124 Table Table Section 10.1: Flash Memory Sector Table 29. The status byte resides in an memory, for details. PSD4235G2V 28). The MCU can read the 28). The identifier for the Table 28). The Protect, for register ...
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... PSD4235G2V Table 29. Status bits DQ7 DQ6 Data Toggle Polling Flag Table 30. Status bits for Motorola DQ15 DQ14 Data Toggle Polling Flag Not guaranteed value, can be read either DQ15-DQ0 represent the Data Bus bits, D15-D0. 3. FS0-FS7/CSBOOT0-CSBOOT3 are active high. ...
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... Sector Erase instructions. The Erase timeout Flag bit (DQ3/DQ11) is reset to ’0’ after a Sector Erase cycle for a period of 100 µs + 20% unless an additional Sector Erase instruction is decoded. After this period, or when the additional Sector Erase instruction is decoded, the Erase timeout flag (DQ3/DQ11) bit is set to 1. 38/124 PSD4235G2V ...
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... PSD4235G2V 8 Programming Flash memory Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all at once or by-sector. Although erasing Flash memory occurs on a sector or device basis, programming Flash memory occurs on a word basis. The primary and secondary Flash memories require the MCU to send an instruction to ...
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... READ DQ5 and DQ7 (DQ13 and DQ15) at Valid Even Address DQ7 (DQ15) Yes = Data7 (Data15) No DQ5 No (DQ13 Yes READ DQ7 (DQ15) DQ7 (DQ15) Yes = Data7 (Data15) No Program Program or Erase or Erase Cycle failed Cycle is complete Issue RESET instruction AI04920 Figure 6 PSD4235G2V shows the Data Toggle ...
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... PSD4235G2V since the Toggle Flag bit (DQ6/DQ14) may have changed simultaneously with the Error Flag bit (DQ5/DQ13, see The Error Flag bit (DQ5/DQ13) is set if either an internal timeout occurred while the embedded algorithm attempted to program the MCU attempted to program a ’1’ bit that was not erased (not erased is logic 0) ...
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... Data toggle flowchart 42/124 START READ DQ5 and DQ6 (DQ13 and DQ14) at Valid Even Address DQ6 No (DQ14) = Toggle Yes DQ5 No (DQ13 Yes READ DQ6 (DQ14) DQ6 No (DQ14) = Toggle Yes Program Program or Erase or Erase Cycle failed Cycle is complete Issue RESET instruction AI04921 PSD4235G2V ...
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... PSD4235G2V 9 Erasing Flash memory 9.1 Flash Bulk Erase The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation of the status register, as described in wrong, the Bulk Erase instruction aborts and the device is reset to the Read Memory mode. During a Bulk Erase, the memory status may be checked by reading the Error Flag bit ...
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... If a Suspend Sector Erase instruction was previously executed, the Erase cycle may be resumed with this instruction. The Resume Sector Erase instruction consists of writing 030h to any even address while an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is high. (See Table 44/124 28.) PSD4235G2V Table 28). This allows reading of ...
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... PSD4235G2V 10 Specific features 10.1 Flash Memory Sector Protect Each sector of primary or secondary Flash memory can be separately protected against Program and Erase cycles. Sector Protection provides additional data security because it disables all Program or Erase cycles. This mode can be activated (or deactivated) through the JTAG-ISP Port or a device programmer. ...
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... SRAM 11 SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is high. SRAM Select (RS0) can contain up to three product terms, allowing flexible memory mapping. SRAM Select (RS0) is configured using PSDsoft Express. 46/124 PSD4235G2V ...
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... PSD4235G2V 12 Memory Select signals The Primary Flash Memory Sector Select (FS0-FS7), Secondary Flash Memory Sector Select (CSBOOT0-CSBOOT3) and SRAM Select (RS0) signals are all outputs of the DPLD. They are defined using PSDsoft Express. The following rules apply to the equations for these signals: ● ...
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... Program Select Enable (PSEN, CNTL2) or Read Strobe (RD, CNTL1). For example, to configure the primary Flash memory in Combined space, bits 2 and 4 of the VM register are set to ’1’ (see Figure 48/124 Highest Priority Level 1 SRAM, I/O, or Peripheral I/O Level 2 Secondary Non-Volatile Memory Level 3 Primary Flash Memory Lowest Priority 9). PSD4235G2V AI02867D Figure 8). ...
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... PSD4235G2V 12.5 80C51XA memory map example See the Application notes for examples. Figure 8. 8031 memory modules - separate space DPLD RS0 CSBOOT0-3 FS0-FS7 PSEN RD Figure 9. 8031 memory modules - combined space DPLD RD VM REG BIT 3 VM REG BIT 4 PSEN VM REG BIT 1 VM REG BIT 2 ...
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... Page register. The eight flip-flops in the register are RESET PGR0 PGR1 PGR2 PGR3 PGR4 PGR5 PGR6 PGR7 PAGE REGISTER PSD4235G2V INTERNAL SELECTS AND LOGIC DPLD AND CPLD PLD AI02871B ...
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... PSD4235G2V 14 Memory ID registers The 8-bit Read-only Memory Status registers are included in the CSIOP space. The user can determine the memory configuration of the PSD device by reading the Memory ID0 and Memory ID1 registers. The content of the registers is defined as shown in Table 26. Memory ID registers ...
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... The Turbo bit in PSD The PLDs in the PSD4235G2V can minimize power consumption by switching to standby when inputs remain unchanged for an extended time of about 70 ns. Resetting the Turbo bit to ’0’ (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs are changing ...
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... PSD4235G2V Table 31. DPLD and CPLD inputs (continued) Input source Page register Macrocell A feedback Macrocell B feedback Flash memory Program Status bit 1. The address inputs are A19-A4 in 80C51XA mode. Input name PGR7-PGR0 MCELLA.FB7-FB0 MCELLB.FB7-FB0 Ready/Busy PLDS Number of signals 53/124 ...
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... PLDS Figure 11. PLD diagram 54/124 PORTS I/O BUS INPUT PLD PSD4235G2V ...
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... PSD4235G2V 16 Decode PLD (DPLD) The DPLD, shown in components. The DPLD can be used to generate the following decode signals: ● 8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms each) ● 4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three product terms each) ● ...
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... OMC). This feature allows efficient implementation of system logic and eliminates the need to connect the data bus to the AND Array as required in most standard PLD macrocell architectures. 56/124 11, the CPLD has the following blocks: PSD4235G2V ...
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... PSD4235G2V Figure 13. Macrocell and I/O port PRODUCT TERMS FROM OTHER MACROCELLS CPLD MACROCELLS PRODUCT TERM ALLOCATOR PRODUCT TERMS POLARITY SELECT PT CLOCK GLOBAL CLOCK CLOCK SELECT PT CLEAR PT OUTPUT ENABLE ( OE ) MACROCELL FEEDBACK I/O PORT INPUT PT INPUT LATCH GATE/CLOCK 17.1 Output macrocell (OMC) Eight of the output macrocells (OMC) are connected to Ports A pins and are named as McellA0-McellA7 ...
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... Port A4 3 Port A5 3 Port A6 3 Port A7 3 Port B0 4 Port B1 4 Port B2 4 Port B3 4 Port B4 4 Port B5 4 Port B6 4 Port B7 4 PSD4235G2V Motorola 16-Bit Data bit for Loading or Loading or Reading ...
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... PSD4235G2V 17.3 Loading and Reading the output macrocells (OMC) The output macrocells (OMC) block occupies a memory location in the MCU address space, as defined by the CSIOP (see macrocells (OMC) can be loaded from the data bus by a MCU. Loading the output macrocells (OMC) with data from the MCU takes priority over internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be overridden by the MCU ...
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... A15. Any latched addresses are routed to the PLDs as inputs. 60/124 ENABLE ( .OE ) PRESET ( .PR ) COMB/REG DIN SELECT CLR CLEAR ( .RE ) PROGRAMMABLE FF ( D/T/JK /SR ) MUX PORT INPUT Section 19: I/O ports). PSD4235G2V INTERNAL DATA BUS DIRECTION REGISTER SELECT MUX PORT DRIVER INPUT MACROCELL Figure 15. The input macrocells (IMC) I/O PIN AI04946 ...
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... PSD4235G2V Input macrocells (IMC) are particularly useful with handshaking communication applications where two processors pass data back and forth through a common mailbox. shows a typical configuration where the Master MCU writes to the Port A Data Out register. This, in turn, can be read by the Slave MCU via the activation of the “Slave-Read” output enable product term ...
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... The output enable of the pin is controlled by either the output enable product term or the Direction register. (See Figure 16. External Chip Select signal ECS PT POLARITY 62/124 Figure 16.) ENABLE (.OE) PT ECS To Port BIT PSD4235G2V Port C or Port F DIRECTION REGISTER PORT PIN AI04927 ...
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... PSD4235G2V Figure 17. Handshaking communication using input macrocells Complex PLD (CPLD) 63/124 ...
Page 64
... R/W DS SIZ0 WEL OE — R/W DS SIZ0 R/W E LSTRB R/W E LSTRB WR RD BHE WRL RD (Note WR RD BHE WR RD BHE WRL RD PSEN (2) WRL RD R/W E BHE PSD4235G2V (1) PD3 PD0 ADIO0 (2) AS — ( WEH AS — ( DBE E A0 (2) 1 (Note ) A0 (2) ALE WRH ALE A0 (2) ALE A0 (2) ...
Page 65
... Figure 18 shows an example of a system using a MCU with a 16-bit multiplexed bus and a PSD4235G2V. The ADIO port on the PSD is connected directly to the MCU address/data bus. Address Strobe (ALE/AS, PD0) latches the address signals internally. Latched addresses can be brought out to Port The PSD drives the ADIO data bus only when one of its internal resources is accessed and Read Strobe (RD, CNTL1) is active ...
Page 66
... Figure 19 shows an example of a system using a MCU with a 16-bit non-multiplexed bus and a PSD4235G2V. The address bus is connected to the ADIO Port, and the data bus is connected to Ports F and G. Ports F and G are in tri-state mode when the PSD is not accessed by the MCU. Should the system address bus exceed sixteen bits, Ports may be used for additional address inputs ...
Page 67
... MCU bus interface examples Figure 20 to Figure 25 and some popular MCUs. The PSD4235G2V Control input pins are labeled as to the MCU function for which they are configured. The MCU bus interface is specified using PSDsoft Express. Table 35. 16-bit data bus with WRH and WRL ...
Page 68
... Figure 20, the Intel 80C196 MCU, which has a 16-bit multiplexed address/data bus, is shown connected to a PSD4235G2V. The Read Strobe (RD, CNTL1), and Write Strobe (WR/WRL, CNTL0) signals are connected to the CNTL pins. When BHE is not used, the PSD can be configured to receive WRL and Write Enable high-byte (WRH/DBE, PD3) from the MCU ...
Page 69
... PSD4235G2V 18.6 MC683xx and MC68HC16 Figure 21 shows a MC68331 with a 16-bit non-multiplexed data bus and 24-bit address bus. The data bus from the MC68331 is connected to Port F (D0-D7) and Port G (D8-D15). The SIZ0 and A0 inputs determine the high/low byte selection. The R/W, DS and SIZ0 signals are connected to the CNTL0-CNTL2 pins. ...
Page 70
... The Philips 80C51XA MCU has a 16-bit multiplexed bus with burst cycles. Address bits (A3- A1) are not multiplexed, while (A19-A4) are multiplexed with data bits (D15-D0). The PSD4235G2V supports the 80C51XA burst mode. The WRH signal is connected to PD3, and WHL is connected to CNTL0. The RD and PSEN signals are connected to the CNTL1 and CNTL2 pins ...
Page 71
... PSD4235G2V 18.8 H8/300 Figure 23 shows an Hitachi H8/2350 with a 16-bit non-multiplexed data bus, and a 24-bit address bus. The H8 data bus is connected to Port F (D0-D7) and Port G (D8-D15). The WRH signal is connected to PD3, and WHL is connected to CNTL0. The RD signal is connected to CNTL1. The connection to the Address Strobe (AS) signal is optional, and is required if the addresses are to be latched ...
Page 72
... PSD in a multiplexed bus configuration. The control signals from the MCU are WR, RD, BHE and ALE, and are routed to the corresponding PSD pins. The C167 has another control signal setting (RD, WRL, WRH, ALE) which is also supported by the PSD. 72/124 Figure 25, the C167CR is shown connected to the PSD4235G2V ...
Page 73
... PSD4235G2V Figure 24. Interfacing the PSD with an MMC2001 VCC_BAR Infineon C167CR 138 XTAL1 U3 CRYSTAL 137 XTAL2 65 P3.0/T0IN 66 P3.1/T6OUT 67 P3.2/CAPIN 68 P3.3/T3OUT 69 P3.4/T3EUD 70 P3.5/T4IN 73 P3.6/T3IN 74 P3.7/T2IN 75 P3.8/MRST 76 P3.9/MTSR 77 P3.10/TXD0 78 P3.11/RXD0 80 P3.13/SCLK 81 P3.15/CLKOUT 27 P5.0/AN0 28 P5.1/AN1 29 P5.2/AN2 30 P5.3/AN3 31 P5.4/AN4 32 P5.5/AN5 33 P5.6/AN6 34 P5.7/AN7 35 P5.8/AN8 36 P5.9/AN9 39 P5.10/AN10/T6UED 40 P5.11/AN11/T5UED 41 P5 ...
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... P1L2 119 P1L1 118 P1L0 140 RSTIN 141 RSTOUT 142 NMI AGND 38 PSD4235G2V A19-A16 AD15-AD0 VCC PSD VCC VCC VCC 31 ADIO0 PF0 ADIO1 32 PF1 ADIO2 33 PF2 ADIO3 34 PF3 ADIO4 35 PF4 ADIO5 36 PF5 ...
Page 75
... PSD4235G2V 19 I/O ports There are seven programmable I/O ports: Ports and G. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft Express or by the MCU writing to on-chip registers in the CSIOP space. The topics discussed in this section are: ● ...
Page 76
... ALE G MACROCELL OUTPUTS EXT CS READ MUX CONTROL REG DIR REG ENABLE PRODUCT TERM ( .OE ) CPLD -INPUT 76/124 DATA OUT Q ADDRESS DATA PSD4235G2V Table 39 shows how and PORT PIN OUTPUT MUX OUTPUT SELECT ENABLE OUT INPUT MACROCELL AI02885 ...
Page 77
... PSD4235G2V 19.3 MCU I/O mode In the MCU I/O mode, the MCU uses the PSD Ports to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD are mapped into the MCU address space. The addresses of the ports are listed in A port pin can be put into MCU I/O mode by writing a ’0’ to the corresponding bit in the Control register (for Ports E, F and G) ...
Page 78
... Yes Yes Yes (1) Control Direction register register setting setting 1 = output, ( input (3) (3) N/A N/A N/A ( N/A N/A N/A N/A N/A N/A N/A N/A PSD4235G2V Port E Port F Port G No Yes No No Yes Yes No Yes No (1) Yes Yes Yes VM register JTAG Enable setting N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A PIO bit = 1 N/A N/A JTAG_Enable N/A N/A ...
Page 79
... PSD4235G2V Table 40. I/O port latched address output assignments Port E MCU (PE3-PE0) 80C51XA Address All other MCU with multiplexed bus a3-a0 1. N/A = Not Applicable. 19.6 Address In mode For MCUs that have more than 16 address signals, the higher addresses can be connected to Port and are routed as inputs to the PLDs. The address input can be latched in the input macrocell (IMC) by Address Strobe (ALE/AS, PD0) ...
Page 80
... G return to the normal Data Port mode. The MCU Reset mode is enabled and configured in PSDsoft Express. The user defines the logic level (data pattern) that will be drive out from Ports F and G during reset. 80/124 PSEL DATA BUS timing. PSD4235G2V PA0 - PA7 AI02886 ...
Page 81
... PSD4235G2V 19.11 Port Configuration registers (PCR) Each Port has a set of Port Configuration registers (PCR) used for configuration. The contents of the registers can be accessed by the MCU through normal READ/WRITE bus cycles at the addresses given in hexadecimal from the base of the CSIOP register. The pins of a port are individually configurable and each bit in the register controls its respective pin ...
Page 82
... NA Open Open Open Drain Drain Drain Slew Slew Slew Rate Rate Rate Open Open Open Drain Drain Drain PSD4235G2V Port pin mode Input Output Port pin mode Input Output Output Output Bit 2 Bit Bit 3 Bit 2 Bit 1 Open Open Open Drain ...
Page 83
... PSD4235G2V 19.14 Port Data registers The Port Data registers, shown in data from the ports. and MCU access for each register type. The registers are described next. 19.15 Data In Port pins are connected directly to the Data In buffer. In MCU I/O input mode, the pin input is read through the Data In buffer. ...
Page 84
... Open Drain/Slew Rate - pins PC7-PC0 can be configured to fast slew rate. Pins PA7- PA0 can be configured to Open Drain mode. 84/124 Port WRITE/READ - prevents loading into a given A, B Macrocell READ - outputs of the input macrocells READ - the output enable control of the port driver PSD4235G2V MCU Access Figure 28. The ports ...
Page 85
... PSD4235G2V Figure 28. Port A, B and C structure DATA OUT Register MCELLA7-MCELLA0 (Port A) MCELLB7-MCELLB0 (Port B) Ext.CS (Port C) READ MUX DIR Register ENABLE PRODUCT TERM ( .OE ) CPLD-INPUT 19.22 Port D - functionality and structure Port D has four I/O pins. See the following functions: ● MCU I/O mode ● ...
Page 86
... Open Drain - pins can be configured in Open Drain mode ● Latched Address output - Provide latched address output. 86/124 DATA OUT Q OUTPUT OUTPUT P SELECT D B DATA IN Q CPLD-INPUT Figure 33: Reset (RESET) timing PSD4235G2V PORT D PIN MUX for more information on JTAG AI04937 Figure 30): ...
Page 87
... PSD4235G2V 19.24 Port F - functionality and structure Port F can be configured to perform one or more of the following functions: ● MCU I/O Mode ● CPLD output - External Chip Select (ECS7-ECS0) can be connected to Port F or Port C. ● CPLD input - direct input to the CPLD, no input macrocells (IMC) ● Latched Address output - Provide latched address output as per ● ...
Page 88
... Register ADDRESS D Q ALE G Ext. CS (Port F) READ MUX CONTROL Register DIR Register ENABLE PRODUCT TERM ( .OE ) 88/124 DATA OUT ADDRESS 15:8 ] OUTPUT MUX OUTPUT SELECT DATA IN CPLD-INPUT (Port F) ISP (Port E) PSD4235G2V PORT Pin ENABLE OUT Configuration Bit AI04938b ...
Page 89
... PSD4235G2V 20 Power management The PSD device offers configurable power saving options. These options may be used individually or in combinations, as follows: ● All memory blocks in a PSD (primary Flash memory, secondary Flash memory, and SRAM) are built with power management technology. In addition to using special silicon design methodology, power management technology puts the memories into standby mode when address/data inputs are not changing (zero DC current) ...
Page 90
... Typical standby current is or the order of µA. This standby current value assumes that there are no transitions on any PLD input. Table 47. Effect of Power-down mode on ports Port function MCU I/O PLD Out Address Out Data port Peripheral I/O 90/124 Figure 31, puts the PSD into Power-down mode by monitoring the PSD4235G2V Pin level No Change No Change Undefined Tri-State Tri-State ...
Page 91
... PSD4235G2V Figure 31. APD unit APD EN PMMR0 BIT 1=1 ALE RESET CSI CLKIN DISABLE Primary and Secondary FLASH Memory and SRAM Table 48. PSD timing and standby current during Power-down mode PLD propagation Mode Power- Normal t down 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo bit ...
Page 92
... PLD AND Array or the macrocells block by setting bits ’1’ in PMMR0. Figure 32. Enable Power-down flowchart 92/124 RESET Enable APD Set PMMR0 Bit OPTIONAL Disable desired inputs to PLD by setting PMMR0 bits 4 and 5 and PMMR2 bits ALE/AS idle No for 15 CLKIN clocks? Yes PSD in Power Down Mode AI04940 PSD4235G2V in Table 68. SLQV ...
Page 93
... PSD4235G2V 20.7 Input control signals The PSD provides the option to turn off the address input (A7-A0) and input control signals (CNTL0, CNTL1, CNTL2, Address Strobe (ALE/AS, PD0) and Write Enable high-byte (WRH/DBE, PD3)) to the PLD to save AC power consumption. These signals are inputs to the PLD AND Array. During Power-down mode, or, if any of them are not being used as part of the PLD logic equation, these control signals should be disabled to save AC power. They are disconnected from the PLD AND Array by setting bits and ’ ...
Page 94
... Power-up and warm reset. ramps up to operating level. Once the PLD is active, CC Power-On Reset Warm Reset Input mode Valid Tri-stated Tri-stated Tri-stated Unchanged PSD4235G2V (minimum NLNH-PO is below V CC period is needed before the device is (minimum 25 μs). NLNH-A Power-down mode Unchanged Depends on inputs to PLD ...
Page 95
... PSD4235G2V Table 50. Status During Power-On Reset, Warm Reset and Power-down mode (continued) Port configuration Cleared to ’0’ by internal Macrocells Flip-flop status Power-On Reset Initialized, based on the selection in PSDsoft (1) VM register Express Configuration menu All other registers Cleared to ’0’ 1. The SR_code and Peripheral Mode bits in the VM register are always cleared to ’0’ on Power-On Reset or Warm Reset. ...
Page 96
... JTAGSEL. This method is used when the Port E JTAG pins are multiplexed with other I/O signals recommended to tie logically the node JTAGSEL to the JEN\ signal on the Flashlink cable when multiplexing JTAG signals. See Application Note 1153 for details. */ 96/124 Table 20 for bit definition. */ PSD4235G2V Table 51). All memory ...
Page 97
... TSTAT behaves the same as Ready/Busy (PE4) described in (PE4). TSTAT is high when the PSD4235G2V device is in READ mode (primary Flash memory and secondary Flash memory contents can be read). TSTAT is low when Flash memory Program or Erase cycles are in progress, and also when data is being written to the secondary Flash memory ...
Page 98
... Programming in-circuit using the JTAG serial interface Table 51. JTAG port signals (continued) Port E pin PE4 PE5 98/124 JTAG signals TSTAT Status TERR Error Flag PSD4235G2V Description ...
Page 99
... PSD4235G2V 23 Initial delivery state When delivered from ST, the PSD device has all bits in the memory and PLDs set to '1.' The PSD Configuration register bits are set to '0.' The code, configuration, and PLD logic are loaded using the programming procedure. Information for programming the device is available directly from ST ...
Page 100
... V Supply voltage CC V Device programmer supply voltage PP Electrostatic discharge voltage (Human Body V ESD model) 1. IPC/JEDEC J-STD-020A. 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω) 100/124 Parameter (1) or Hi-Z) OH (2) PSD4235G2V Min. Max. Unit –65 150 °C 235 °C –0.6 4.0 V –0.6 4.0 V –0.6 13.5 V –2000 ...
Page 101
... PSD4235G2V 25 DC and AC parameters These tables describe the AD and DC parameters of the PSD4235G2V: ● DC Electrical Specification ● AC timing Specification – PLD timing Combinatorial timing Synchronous clock mode Asynchronous clock mode Input macrocell timing – MCU timing READ timing WRITE timing Peripheral mode timing ...
Page 102
... Ipwrdown x %pwrdown + % normal x (%flash x 1.2 mA/MHz x Freq ALE + %SRAM x 0.8 mA/MHz x Freq ALE + % PLD x 1.1 mA/MHz x Freq PLD + #PT x 200 µA/PT µA x 0.90 + 0.1 x (0.8 x 1.2 mA/MHz x 4 MHz + 0.15 x 0.8 mA/MHz x 4 MHz + 1.1 mA/MHz x 8 MHz + 54 x 0.2 mA/PT µA + 0.1 x (3.84 + 0.48 + 8.8 + 10.8 mA µA + 0.1 x 23. µ 2.43 mA PSD4235G2V = 3.0 V (with Turbo mode on) CC (ac (dc (1) ...
Page 103
... PSD4235G2V Table 54. Example of PSD typical power calculation at V (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory Access % SRAM access % I/O access % Normal % Power-down Mode (from fitter report total product terms Turbo Mode I total CC 1. This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based ...
Page 104
... Address Valid to ALE Invalid. AVLX Table 57. AC signal behavior symbols for PLD timings Letter 104/124 Parameter (1) Description output Time Logic level low or ALE Logic level high Valid No Longer a Valid Logic level Float PSD4235G2V Min. Max. Unit 3.0 3.6 V –40 85 ° °C Description ...
Page 105
... PSD4235G2V Table 58. AC measurement conditions Symbol C Load Capacitance L 1. Output Hi-Z is defined as the point where data out is no longer driven. (1) Table 59. Capacitance Symbol Parameter C Input capacitance (for input pins) IN Output capacitance (for C OUT input/output pins) C Capacitance (for CNTL2/V VPP 1. Sampled only, not 100% tested. ...
Page 106
... –20µ 4.5V 2 –2 mA 4.5V 2 (2)(3) CSI >V –0. < V < V – 0.45 < V < V –10 OUT CC PSD4235G2V AI03102 Typ. Max. Unit 0.2V –0 2.3 V 0.01 0.1 V 0.15 0.45 V 2. 100 µA ± ...
Page 107
... PSD4235G2V Table 60. DC characteristics (continued) Symbol Parameter PLD Only Operating I (DC) CC Supply 5 (Note ) Current Flash memory SRAM PLD AC Adder Flash memory AC Adder I (AC) CC SRAM AC Adder 1. Reset (RESET) has hysteresis CSI deselected or internal Power-down mode is active. 3. PLD is in non-Turbo mode, and none of the inputs are switching. ...
Page 108
... Min Max 1/( 24 1/(t +t –10) 32 1/( 45 Clock input 11 Clock input 11 Clock input 23 Any macrocell PSD4235G2V -12 Fast Slew Turbo PT rate Off Min Max (1) Aloc -12 Fast Slew Turbo PT rate Off (1) Min Max Aloc 20.4 25.6 35 – ...
Page 109
... PSD4235G2V Table 63. CPLD macrocell Asynchronous clock mode timing Symbol Parameter Conditions Maximum frequency 1/(t External Feedback Maximum frequency f MAXA Internal 1/(t SA Feedback (f ) CNTA Maximum frequency 1/(t Pipelined Data t Input setup time SA t Input Hold time HA Clock input high t CHA time Clock input low t CLA ...
Page 110
... Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to t 110/124 tARPW tARP tCHA tCLA tSA tHA t t INH INL -90 Conditions Min Max ( PSD4235G2V AI02864 tCOA AI02859 t INO -12 PT Turbo Aloc Off Min Max and t . AVLX LXAX Unit ...
Page 111
... PSD4235G2V Table 65. Program, WRITE and Erase times Symbol Flash Program (1) Flash Bulk Erase Flash Bulk Erase (not pre-programmed) t Sector Erase (pre-programmed) WHQV3 t Sector Erase (not pre-programmed) WHQV2 t Byte Program WHQV1 Program / Erase Cycles (per Sector) t Sector Erase timeout WHWLO DQ7 Valid to output (DQ7-DQ0) Valid (Data ...
Page 112
... LXAX t LVLX ADDRESS VALID t AVQV ADDRESS VALID t SLQV t RLQV t RLRH t THEH ADDRESS OUT Conditions Min 22 7 (1) 8 (2) ( PSD4235G2V DATA VALID DATA VALID t RHQX tRHQZ t EHEL t ELTL AI02895 -90 -12 Turbo Off Max Min Max 120 + 20 90 120 ...
Page 113
... PSD4235G2V Table 66. READ timing (continued) Symbol Parameter t R/W Hold time After Enable ELTL Address input Valid to t AVPV Address output Delay 1. Any input used to select an internal PSD function timing has the same timing as DS, LDS, and UDS signals and PSEN have the same timing. ...
Page 114
... AVLX t LXAX t LVLX ADDRESS VALID t AVWL ADDRESS VALID t SLWL t WLWH t THEH t AVPV ADDRESS OUT Conditions (1) (1) (1)(2) (2) (2) (2)(3) (2) (2) (2)(4) PSD4235G2V DATA VALID DATA VALID t DVWH t WHDX t WHAX t EHEL t ELTL t WLMV t WHPV STANDARD MCU I/O OUT AI02896 -90 -12 Min Max Min Max ...
Page 115
... PSD4235G2V Table 67. WRITE timing Symbol Parameter Trailing edge Port output t WHPV Valid Using I/O Port Data register Data Valid to Port output Valid t Using macrocell register DVMV Preset/Clear Address input Valid to Address t AVPV Output Delay WR Valid to Port output Valid Using t WLMV Macrocell register Preset/Clear 1 ...
Page 116
... Reset (RESET) timing Symbol Parameter t RESET Active low time NLNH t Power-on Reset Active low time NLNH–PO 116/124 Conditions Min (1) (2)( (4) Conditions (1) (2) (1) t OPR Conditions (1) PSD4235G2V -90 -12 Turbo Off Max Min Max ...
Page 117
... PSD4235G2V Table 70. Reset (RESET) timing Symbol Parameter (2) t Warm Reset NLNH–A t RESET high to Operational Device OPR 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ mode. ...
Page 118
... ISC Port Valid output to t ISCPVZ High-Impedance 1. For non-PLD Programming, Erase or in ISC by-pass mode. 2. For Program or Erase PLD only. 118/124 -90 Conditions Min Max 15 ( (2) 240 240 PSD4235G2V -12 Unit Min Max 12 MHz MHz 240 ns 240 ...
Page 119
... PSD4235G2V 26 Package mechanical In order to meet environmental requirements, ST offers this device in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Figure 49. LQFP80 - 80-lead plastic thin, quad, flat package outline 1 ...
Page 120
... LQFP80 - 80-lead plastic thin, quad, flat package mechanical data Symb L1 k ccc 1. Values in inches are converted from mm and rounded to 4 decimal digits. 120/124 mm Typ Min Max 1.000 – – 0° 7° 0.080 PSD4235G2V (1) inches Typ Min Max 0.0390 – – 3.5 0° 7° – – 0.003 ...
Page 121
... I = –40 to 85°C (Industrial) Option T = Tape & Reel Packing 1. The 5.0V±10% devices are not covered by this datasheet, but by the PSD4235G2 datasheet. For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. ...
Page 122
... Pin assignments Appendix A Pin assignments Table 75. PSD4235G2V LQFP80 Pin Pin Pin assignments num. num. 1 PD2 21 2 PD3 22 3 AD0 23 4 AD1 24 5 AD2 25 6 AD3 26 7 AD4 27 8 GND AD5 30 11 AD6 31 12 AD7 32 13 AD8 33 14 AD9 ...
Page 123
... PSD4235G2V 28 Revision history Table 76. Document revision history Date 14-Dec-2001 12-Feb-2009 Revision Document for the 3.3V±10% range separated out from the data 1 sheet on the 5V±10% range Document reformatted. Updated datasheet status to “Full Datasheet”. Changed TQFP80 to LQFP80, updated 2 plastic thin, quad, flat package ...
Page 124
... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 124/124 Please Read Carefully: © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com PSD4235G2V ...