PSD4235G2V-10U STMICROELECTRONICS [STMicroelectronics], PSD4235G2V-10U Datasheet
PSD4235G2V-10U
Related parts for PSD4235G2V-10U
PSD4235G2V-10U Summary of contents
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... Erase/WRITE Cycles of Flash Mem- ory – 1,000 Erase/WRITE Cycles of PLD – 15 Year Data Retention Single Supply Voltage – 3V (+20%/–10%) Memory Speed – 100ns Flash memory and SRAM access time for (+20%/–10%) CC – 90ns Flash memory and SRAM access time for V = 3.3V (+/–10%) CC Figure 1 ...
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... Logic Diagram (Figure 2 Pin Names (Table 1.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TQFP80 Connections (Figure 3 TQFP80 Pin Description (Table 2 PSD Block Diagram (Figure 4 PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MCU Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ISP via JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PLD I/O (Table 3 JTAG Signals on Port E (Table 4 In-System Programming (ISP) ...
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... Flash Memory Protection Register 1 (Table 18 Flash Memory Protections Register 2 (Table 19 Flash Boot Protection Register (Table 20 JTAG Enable Register (Table 21 Page Register (Table 22 PMMR0 Register (Table 23.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PMMR2 Register (Table 24.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 VM Register (Table 25 Memory_ID0 Register (Table 26 Memory_ID1 Register (Table 27 ...
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... RESET Reset (RESET) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 MEMORY SELECT SIGNALS Example Priority Level of Memory and I/O Components (Figure 8 Configuration Modes for MCUs with Separate Program and Data Spaces . . . . . . . . . . . . . . . . . . . 36 Combined Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 80C31 Memory Map Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8031 Memory Modules – Separate Space (Figure 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8031 Memory Modules – ...
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Loading and Reading the Output Macrocells (OMC ...
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PSD4256G6V Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Power-on RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Warm RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 I/O Pin, Register and PLD Status at RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 RESET of Flash Memory Erase and Program Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Status During Power-on RESET, Warm RESET, and Power-down Mode (Table 51 Reset (RESET) Timing (Figure 34 PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 75 Standard JTAG Signals ...
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PSD4256G6V DC AND AC PARAMETERS ...
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... First time programming. How do I get firmware into the Flash memory the very first time? JTAG is the answer. Program the blank PSD with no MCU involvement. Inventory build-up of pre-programmed devic- es ...
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PSD4256G6V Figure 2. Logic Diagram CNTL0- CNTL2 PSD4xxxGx 16 AD0-AD15 RESET V SS 10/100 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Table 1. ...
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Figure 3. TQFP80 Connections PD2 1 PD3 2 AD0 3 AD1 4 AD2 5 AD3 6 AD4 7 GND AD5 10 AD6 11 AD7 12 AD8 13 AD9 14 AD10 15 AD11 16 AD12 17 AD13 ...
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... Active Low input. Resets I/O Ports, PLD Macrocells and some of the Configuration RESET 39 I Registers and JTAG registers. Must be Low at Power-up. RESET also aborts any Flash memory Program or Erase cycle that is currently in progress. These pins make up Port A. These port pins are configurable and can have the I/O following functions: CMOS 1. MCU I/O – ...
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... Transparent PLD input (can also be PLD input for address A16 and above). PD2 PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and Open Drain I/O PD3 pin of Port D. This port pin can be configured to have the following functions: CMOS 1. MCU I/O – ...
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PSD4256G6V Pin Name Pin Type PE4 pin of Port E. This port pin can be configured to have the following functions: I/O CMOS 1. MCU I/O – standard output or input port. PE4 Latched address output. Open ...
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Figure 4. PSD Block Diagram Note: Additional address lines can be brought in to the device via Port This is preliminary information on a new product now in development or undergoing evaluation. Details are ...
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... Blocks“ on page 25. The 8Mbit primary Flash memory is the main memory of the PSD divided into 16 equally- sized sectors that are individually selectable. The 512Kbit secondary Flash memory is divided into 4 sectors. Each sector is individually select- able ...
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... MCU 256 times. The paged address can be used as part of the address space to access external memory and peripherals, or in- ternal memory and I/O. The Page Register can also be used to change the address mapping of Table 5. Methods of Programming Different Functional Blocks of the PSD ...
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... The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD pin functions and memory map information. The general design flow is shown in Figure 5. PSDsoft is available from our web site (the address is given Figure 5. PSDsoft Development Tool ...
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... Flash memory Sector Protection Enables JTAG Port Power Management Register 0 Power Management Register 2 Page Register Places PSD memory areas in Program and/ or Data space on an individual basis. Read only – SRAM and Primary memory size Read only – Secondary memory type and size 19/100 ...
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PSD4256G6V REGISTER BIT DEFINITION All the registers of the PSD are included here, for reference. Detailed descriptions of these registers can be found in the following sections. Table 7. Data-In Registers - Ports and ...
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... Sec13_Prot Note: Bit Definitions (Read only register): Sec<i>_Prot 1 = Primary Flash memory Sector <i> is write protected. Sec<i>_Prot 0 = Primary Flash memory Sector <i> is not write protected. This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Bit 4 ...
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... Note: Bit Definitions: Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write protected. Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write protected. Security_Bit 0 = Security Bit in device has not been set. Security_Bit 1 = Security Bit in device has been set. Table 21. JTAG Enable Register ...
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... RD cannot access Secondary NVM in 80C51XA modes can access Secondary NVM in 80C51XA modes. FL_data cannot access Primary Flash memory in 80C51XA modes can access Primary Flash memory in 80C51XA modes. Peripheral mode 0 = Peripheral mode of Port F is disabled Peripheral mode of Port F is enabled. ...
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... There is no Primary Flash memory 1h = Primary Flash memory size is 256Kbit 2h = Primary Flash memory size is 512Kbit 3h = Primary Flash memory size is 1Mbit 4h = Primary Flash memory size is 2Mbit 5h = Primary Flash memory size is 4Mbit 6h = Primary Flash memory size is 8Mbit S_size[3: There is no SRAM 1h = SRAM size is 16Kbit ...
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... The PSD has the following memory blocks: – Primary Flash memory – Secondary Flash memory – SRAM The Memory Select signals for these blocks origi- nate from the Decode PLD (DPLD) and are user- defined in PSDsoft. Table 28 summarizes the sizes and organizations of the memory blocks ...
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... READ operations, just as it would read a ROM de- vice. However, Flash memory can only be erased and programmed using specific instructions. For example, the MCU cannot write a single byte di- rectly to Flash memory as one would write a byte Data space to RAM. To program a word into Flash memory, the MCU must execute a Program instruction, then test the status of the Programming event ...
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... The MCU must retrieve, for example, the code from the secondary Flash memory when reading the Sector Protection Status of the primary Flash memory. 14. All WRITE bus cycles in an instruction are byte-WRITE to an even address (XA4Ah or X554h). A Flash memory Program bus cycle writes a word to an even address. ...
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... Flash memory is to receive and exe- cute the instruction. The primary Flash memory is selected if any one of its Sector Select signals (FS0-FS15) is High, and the secondary Flash memory is selected if any one of its Sector Select signals (CSBOOT0-CSBOOT3) is High. Power-up Condition The PSD internal logic is reset upon Power-up to the READ Mode ...
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... This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. that DQ15-DQ8 is an even byte for Motorola MCUs with a 16-bit data bus. For Flash memory, the MCU can perform a READ operation to obtain these status bits while an Erase or Program instruction is being executed by the embedded algorithm. See the section entitled “ ...
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... Error Flag (DQ5) – DQ13 for Motorola During a normal Program or Erase cycle, the Error Flag Bit (DQ5/DQ13) is reset to ’0.’ This bit is set to ’1’ when there is a failure during a Flash memory Program, Sector Erase, or Bulk Erase cycle. In the case of Flash memory programming, the Er- ...
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... It is suggested (as with all Flash memories) to read the location again after the embedded program- ming algorithm has completed, to compare the word that was written to the Flash memory with the word that was intended to be written. When using the Data Polling method during an Erase cycle, Figure 6 still applies ...
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... Unlock Bypass Reset instruc- tion. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are “Don’t care” for both cycles. The Flash memory then re- turns to READ Mode. Figure 7. Data Toggle Flowchart ...
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... READ Mode Suspend Sector Erase instruction was exe- cuted, the following rules apply: – Attempting to read from a Flash memory sector that was being erased outputs invalid data. – Reading from a Flash memory sector that was not being erased is valid. ...
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... READ Mode recommended that the Reset (RESET) pulse (except for Power On Reset, as described on page 74 least that the Flash memory is always ready for the MCU to retrieve the bootstrap instructions after the RESET cycle is complete. ...
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... Flash memory segment 0. Any address greater than 9FFFh ac- cesses the primary Flash memory segment 0. You can see that half of the primary Flash memory seg- ment 0 and one-fourth of secondary Flash memory segment 0 cannot be accessed in this example. Also note that an equation that defined FS1 to any- where in the range of 8000h to BFFFh would not be valid ...
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... VM register to be set to 0Ch (see Figure 9). Figure 9. 8031 Memory Modules – Separate Space DPLD RS0 CSBOOT0-3 FS0-FS15 PSEN RD Figure 10. 8031 Memory Modules – Combined Space DPLD RD VM REG BIT 3 VM REG BIT 4 PSEN VM REG BIT 1 VM REG BIT 2 VM REG BIT 0 36/100 This is preliminary information on a new product now in development or undergoing evaluation ...
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... Sector Select CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations. If memory paging is not needed not all eight page register bits are needed for memory paging, Figure 11. Page Register MEMORY ID REGISTERS The 8-bit “Read only” Memory Status Registers are included in the CSIOP space. The user can ...
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... Figure 12, page 39 shows the configuration of the PLDs. The DPLD performs address decoding for internal components, such as memory, registers, and I/O ports Select signals. The CPLD can be used for logic functions, such as loadable counters and shift registers, state ma- chines, and encoding and decoding logic ...
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... INPUT MACROCELL and INPUT PORTS 24 12 PORT D and PORT F INPUTS This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 16 PRIMARY FLASH MEMORY SELECTS 4 SECONDARY NON-VOLATILE MEMORY SELECTS 3 SRAM SELECT 1 CSIOP SELECT 2 PERIPHERAL SELECTS 1 JTAG SELECT ...
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... The DPLD can be used to generate the following decode signals: 8 Sector Select (FS0-FS15) signals for the primary Flash memory (three product terms each) 4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three product terms each) Figure 13. DPLD Logic Array I /O PORTS (PORT A,B,C,F) MCELLA.FB [7:0] (FEEDBACKS) MCELLB.FB [7:0] (FEEDBACKS) ...
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COMPLEX PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate eight External ...
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PSD4256G6V Output Macrocell (OMC) Eight of the Output Macrocells (OMC) are con- nected to Ports A pins and are named as McellA0- McellA7. The other eight Macrocells are connect Ports B pins and are named as McellB0- McellB7. ...
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... Loading and Reading the Output Macrocells (OMC) The Output Macrocells (OMC) block occupies a memory location in the MCU address space, as defined by the CSIOP (see Figure 21 to Figure 30 for examples of the basic connections between the PSD and some popular MCUs). The PSD Control input pins are labeled as to the MCU function for which they are configured ...
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PSD4256G6V Figure 15. CPLD Output Macrocell MASK REG. MACROCELL ALLOCATOR POLARITY PT CLK CLKIN FEEDBACK ( .FB ) 44/100 This is preliminary information on a new product now in development or undergoing evaluation. ...
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Input Macrocells (IMC) The CPLD has 24 Input Macrocells (IMC), one for each pin on Ports A, B, and C. The architecture of the Input Macrocells (IMC) is shown in Figure 16. The Input Macrocells (IMC) are individually config- urable, ...
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PSD4256G6V External Chip Select The CPLD also provides eight External Chip Se- lect (ECS0-ECS7) outputs that can be used to se- lect external devices. Each External Chip Select (ECS0-ECS7) consists of one product term that can be configured active High ...
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MCU BUS INTERFACE The “no-glue logic” MCU Bus Interface block can be directly connected to most popular 8-bit and 16- bit MCUs and their control signals. Key MCUs, Table 34. 16-bit MCUs and Their Control Signals MCU 68302, 68306, MMC2001 ...
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PSD4256G6V PSD Interface to a Multiplexed Bus Figure 19 shows an example of a system using an MCU with a multiplexed bus and a PSD4256G6V. The ADIO port on the PSD is connected directly to the MCU address/data bus. Address ...
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PSD Interface to a Non-Multiplexed, 16-bit Bus Figure 20 shows an example of a system using an MCU with a 16-bit, non-multiplexed bus and a PSD4256G6V. The address bus is connected to the ADIO Port, and the data bus is ...
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PSD4256G6V Data Byte Enable Reference for a 16-bit Bus MCUs have different data byte orientations. Table 35 to Table 38 show how the PSD4256G6V inter- prets byte/word operations in different bus WRITE configurations. Even-byte refers to locations with address A0 ...
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In Figure 21, the Intel 80C196 MCU, which has a 16-bit multiplexed address/data bus, is shown connected to a PSD4256G6V. The READ Strobe (RD, CNTL1), and WRITE Strobe (WR/WRL, CNTL0) signals are connected to the CNTL pins. ...
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PSD4256G6V MC683xx and MC68HC16 Figure 22 shows a MC68331 with a 16-bit non- multiplexed data bus and 24-bit address bus. The data bus from the MC68331 is connected to Port F (D0-D7) and Port G (D8-D15). The SIZ0 and A0 ...
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... This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. The 80C51XA improves bus throughput and per- formance by issuing burst cycles to retrieve codes from memory. In burst cycles, address A19-A4 are latched internally by the PSD, while the 80C51XA drives the A3-A1 signals to retrieve sequentially bytes of code ...
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PSD4256G6V H8/300 Figure 24 shows an Hitachi H8/2350 with a 16-bit non-multiplexed data bus, and a 24-bit address bus. The H8 data bus is connected to Port F (D0- D7) and Port G (D8-D15). Figure 24. Interfacing the PSD with ...
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MMC2001 The Motorola MCORE MMC2001 MCU has a MOD input pin that selects internal or external boot ROM. The PSD can be configured as the external flash boot ROM or as extension to the internal ROM (see Figure 25, page ...
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PSD4256G6V Figure 25. Interfacing the PSD with an MMC2001 VCC_BAR Infineon C167CR 138 XTAL1 U3 CRYSTAL 137 XTAL2 65 P3.0/T0IN 66 P3.1/T6OUT 67 P3.2/CAPIN 68 P3.3/T3OUT 69 P3.4/T3EUD 70 P3.5/T4IN 73 P3.6/T3IN 74 P3.7/T2IN 75 P3.8/MRST 76 P3.9/MTSR 77 P3.10/TXD0 ...
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Figure 26. Interfacing the PSD with a C167CR Vcc 144136129109 VccVccVccVccVccVccVccVccVccVcc 138 XTAL1 C167CR 137 XTAL2 65 P3.0/T0IN 66 P3.1/T6OUT 67 P3.2/CAPIN 68 P3.3/T3OUT 69 P3.4/T3UED 70 P3.5/T4IN 73 P3.6/T3IN 74 P3.7/T2IN 75 P3.8/MRST ...
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PSD4256G6V I/O PORTS There are seven programmable I/O ports: Ports and G. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft or by the ...
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Figure 27. General I/O Port Architecture DATA OUT REG ADDRESS D ALE G MACROCELL OUTPUTS EXT CS READ MUX D B CONTROL REG DIR REG ENABLE PRODUCT TERM ( .OE ) CPLD - INPUT ...
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... Ports E, F and G for various MCUs. Note: Do not drive address signals with Address Out Mode to an external memory device in- tended for the MCU to Boot from the external de- vice. The MCU must first Boot from PSD memory so the Direction and Control register bits can be set ...
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Table 40. Port Operating Mode Settings Mode Defined in PSDsoft MCU I/O Declare pins only Declare pins and PLD I/O Logic equations Selected for MCU Data Port (Port F, G) with non-multiplexed bus Address Out Declare pins only (Port E, ...
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... Macrocell (IMC) by Address Strobe (ALE/AS, PD0). Any input that is included in the DPLD equa- tions for the primary Flash memory, secondary Flash memory or SRAM is considered ad- dress input. Data Port Mode Ports F and G can be used as a data bus port for a MCU with a non-multiplexed address/data bus ...
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JTAG In-System Programming (ISP) Port E is JTAG compliant, and can be used for In- System Programming (ISP). You can multiplex JTAG operations with other functions on Port E because In-System Programming (ISP) is not per- formed during normal system ...
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PSD4256G6V Direction Register The Direction Register controls the direction of data flow in the I/O Ports. Any bit set the Di- rection Register causes the corresponding pin output, and any bit set to 0 ...
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Port Data Registers The Port Data Registers, shown in Table 47, are used by the MCU to write data to or read data from the ports. Table 47 shows the register name, the ports having each register type, and MCU ...
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PSD4256G6V Enable Out The Enable Out register can be read by the MCU. It contains the output enable values for a given port indicates the driver is in output mode indicates the driver is in tri-state ...
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... Address Strobe (ALE/AS, PD0) CLKIN (PD1) as input to the Macrocells Flip- flops and APD counter PSD Chip Select Input (CSI, PD2). Driving this signal High disables the Flash memory, SRAM and CSIOP. WRITE-Enable High-byte (WRH, PD3) input DBE input from a MC68HC912. ...
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PSD4256G6V Port E – Functionality and Structure Port E can be configured to perform one or more of the following functions (see Figure 31, page 69): MCU I/O Mode In-System Programming (ISP) – JTAG port can be enabled for programming/erase ...
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Figure 31. Port E, F, and G Structure DATA OUT Register ADDRESS D Q ALE G Ext. CS (Port F) READ MUX CONTROL Register DIR Register ENABLE PRODUCT ...
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... POWER MANAGEMENT The PSD device offers configurable power saving options. These options may be used individually or in combinations, as follows: All memory blocks in a PSD (primary Flash memory, secondary Flash memory, and SRAM) are built with power management technology. In addition to using special silicon design ...
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... DETECTION ALE RESET EDGE CSI DETECT CLKIN DISABLE Primary and Secondary FLASH Memory and SRAM Table 49. PSD Timing and Standby Current During Power-down Mode Mode PLD Propagation Delay Power-down Normal t (Note PD Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo bit. ...
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... O blocks for READ or WRITE operations involving the PSD. A High on PSD Chip Select Input (CSI, PD2) disables the primary Flash memory, second- ary Flash memory, and SRAM, and reduces the PSD power consumption. However, the PLD and 72/100 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. ...
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Input Control Signals The PSD provides the option to turn off the ad- dress input (A7-A0) and input control signals (CNTL0, CNTL1, CNTL2, Address Strobe (ALE/ AS, PD0) and WRITE-Enable High-byte (WRH/ DBE, PD3)) to the PLD to save AC ...
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... OPR first memory access is allowed. The PSD Flash memory is reset to the READ Mode upon Power-up. Sector Select (FS0-FS15 and CSBOOT0-CSBOOT3) must all be Low, WRITE Strobe (WR/WRL, CNTL0) High, during Power-on RESET for maximum security of the ...
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... RESET PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE The JTAG Serial Interface on the PSD can be en- abled on Port E (see Table 52). All memory blocks (primary Flash memory and secondary Flash memory), PLD logic, and PSD Configuration bits may be programmed through the JTAG-ISC Serial Interface ...
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... Flash memory. INITIAL DELIVERY STATE When delivered from ST, the PSD device has all bits in the memory and PLDs set to 1. The PSD Configuration Register bits are set to 0. The code, configuration, and PLD logic are loaded using the 76/100 This is preliminary information on a new product now in development or undergoing evaluation ...
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... Also, the supply power is considerably different if the Turbo bit is 0. The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Figure 35 shows the PLD mA/MHz as a function of the number of Product Terms (PT) used. In the PLD timing parameters, add the required delay when Turbo bit is 0 ...
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... Turbo Mode I total CC This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based mA. 78/100 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. = 3.0V (with Turbo Mode On) ...
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... Turbo Mode I total CC This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based mA. This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. = 3.0V (with Turbo Mode Off) CC ...
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PSD4256G6V MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings” table may cause per- manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions ...
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DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de- rived from tests performed ...
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PSD4256G6V Table 59. Capacitance Symbol Parameter C Input Capacitance (for input pins) IN Output Capacitance (for input/ C OUT output pins) C Capacitance (for CNTL2/V VPP Note: 1. Sampled only, not 100% tested. 2. Typical values are for T = ...
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... Flash memory SRAM PLD AC Adder I (AC) CC Flash memory AC Adder 5 (Note ) SRAM AC Adder Note: 1. Reset (RESET) has hysteresis CSI deselected or internal PD is active. 3. PLD is in non-Turbo mode, and none of the inputs are switching. 4. Please see Figure 35, page 77 for the PLD current calculation. ...
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PSD4256G6V Figure 39. Input to Output Disable / Enable INPUT INPUT TO OUTPUT ENABLE/DISABLE Table 61. CPLD Combinatorial Timing Symbol Parameter CPLD Input Pin/Feedback CPLD Combinatorial Output CPLD Input to CPLD Output t EA Enable CPLD Input ...
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Table 63. CPLD Macrocell Asynchronous Clock Mode Timing Symbol Parameter Maximum Frequency External Feedback Maximum Frequency f MAXA Internal Feedback (f CNTA Maximum Frequency Pipelined Data t Input Setup Time SA t Input Hold Time HA t Clock High Time ...
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PSD4256G6V Figure 42. Asynchronous Clock Mode Timing (product term clock) CLOCK INPUT REGISTERED OUTPUT Figure 43. Input Macrocell Timing (Product Term Clock) PT CLOCK INPUT OUTPUT AI03101 Table 64. Input Macrocell Timing Symbol Parameter t Input Setup Time IS t ...
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Table 65. Program, WRITE and Erase Times Symbol Flash Program 1 Flash Bulk Erase Flash Bulk Erase (not pre-programmed) t Sector Erase (pre-programmed) WHQV3 t Sector Erase (not pre-programmed) WHQV2 t Byte Program WHQV1 Program / Erase Cycles (per Sector) ...
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PSD4256G6V Figure 45. READ Timing Diagram ALE /AS A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI RD (PSEN, DS) E R/W t AVPV Note and t are not required for 80C251 in Page Mode or 80C51XA ...
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Table 66. READ Timing Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid to Data Valid AVQV t CS Valid to Data Valid SLQV RD to Data ...
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PSD4256G6V Figure 46. WRITE Timing Diagram ALE /AS A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR (DS 90/100 This is preliminary information on a new product now in development or undergoing evaluation. Details are ...
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... Assuming data is stable before active WRITE signal. 5. Assuming WRITE is active before data becomes valid. 6. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory. 7. tWHAX when writing to the Output Macrocell Registers. ...
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PSD4256G6V Figure 47. Peripheral I/O READ Timing Diagram ALE /AS A/D BUS CSI RD Table 68. Port F Peripheral Data Mode READ Timing Symbol Parameter t Address Valid to Data Valid AVQV–PF t CSI Valid to Data Valid SLQV–PF RD ...
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... Warm RESET Active Low Time NLNH–A t RESET High to Operational Device OPR Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode. Figure 48. Reset (RESET) Timing Diagram V (min ...
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PSD4256G6V Figure 49. ISC Timing Diagram t TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO Table 73. ISC Timing Symbol Parameter Clock (TCK, PC1) Frequency (except for t ISCCF PLD) t Clock (TCK, PC1) High Time (except for PLD) ISCCH t Clock ...
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... Device Type PSD42 = Flash PSD with CPLD SRAM Size 3 = 64Kbit 5 = 256Kbit Flash Memory Size 5 = 4Mbit 6 = 8Mbit I/O Count I/O 2nd Non-Volatile Memory 2 = 256Kbit Flash Memory 6 = 512Kbit Flash Memory Operating Voltage 2.7 to 3.6V CC Speed 90 = 90ns 10 = 100ns 12 = 120ns Package U = TQFP80 Temperature Range blank = 0 to 70°C (Commercial – ...
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PSD4256G6V PACKAGE MECHANICAL INFORMATION Figure 50. TQFP80 – 80-lead Plastic Quad Flatpack Package Outline QFP-A Note: Drawing is not to scale. 96/100 This is preliminary information on a new product now in development or undergoing evaluation. Details ...
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Table 75. TQFP80 – 80-lead Plastic Quad Flatpack Package Mechanical Data Symb Typ – – A2 1.40 0. – D 14.00 D1 12.00 D2 9.50 E 14.00 E1 12.00 E2 9.50 e 0.50 L 0.60 L1 ...
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PSD4256G6V Table 76. Pin Assignments - PSD4256G6V TQFP80 Pin Pin No. Assign ments 1 PD2 2 PD3 3 AD0 4 AD1 5 AD2 6 AD3 7 AD4 8 GND AD5 11 AD6 12 AD7 13 AD8 ...
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REVISION HISTORY Table 77. Document Revision History Date Rev. 06-Aug-2001 1.0 Document written 13-Sep-2001 1.1 Package mechanical data updated Added 100ns specification; removed 90 and 120 ns specifications. Updated AC specification 14-Dec-2001 1.2 and Port C and F functions 06-Dec-2002 ...
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PSD4256G6V Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its ...