LT3071EUFD LINER [Linear Technology], LT3071EUFD Datasheet

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FeAtures Output Current Dropout Voltage: 85mV Typical n Digitally Programmable V : 0.8V to 1.8V n OUT Analog Output Margining: ±10% Range n Low Output Noise: 25µV (10Hz to 100kHz) n RMS Parallel Multiple Devices for 10A or ...

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... LEAD FREE FINISH TAPE AND REEL LT3071EUFD#PBF LT3071EUFD#TRPBF LT3071IUFD#PBF LT3071IUFD#TRPBF LT3071MPUFD#PBF LT3071MPUFD#TRPBF LEAD BASED FINISH TAPE AND REEL LT3071EUFD LT3071EUFD#TR LT3071IUFD LT3071IUFD#TR LT3071MPUFD LT3071MPUFD#TR Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/  pin conFigurAtion VIOC ...

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T otherwise noted. PARAMETER CONDITIONS IN Pin Voltage Range V ≥ BIAS Pin Voltage Range (Note 3) Regulated Output Voltage V = 0.8V, 10mA ≤ I OUT V = 0.9V, 10mA ≤ I OUT V = 1V, 10mA ≤ I OUT V = 1.1V, 10mA ≤ I OUT V = 1.2V, 10mA ≤ I OUT V = 1.5V, 10mA ≤ I OUT V = 1.8V, 10mA ≤ I OUT ...

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LT3071 electricAl chArActeristics temperature range, otherwise specifications are at T otherwise noted. PARAMETER CONDITIONS V Undervoltage Lockout V Rising BIAS BIAS V Falling BIAS V -V Servo Voltage by VIOC IN OUT VIOC Output Current Input Threshold (Logic-0 State), Input Falling IL V ...

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Dropout Voltage vs I OUT 150 OUT(NOMINAL 25°C J 120 1.8V OUT V = 3.3V BIAS 0.8V OUT V = 2.5V BIAS ...

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LT3071 typicAl perFormAnce chArActeristics Output Voltage (1.8V) vs Temperature 1.818 I = 10mA LOAD 1.814 1.810 1.806 1.802 1.798 1.794 1.790 1.786 1.782 –75 –50 – 100 125 150 TEMPERATURE (°C) 3071 G10 BIAS Pin Current ...

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EN Pin Thresholds 2 2.5V BIAS 1.8 1.6 1.4 EN PIN RISING 1.2 1.0 EN PIN FALLING 0.8 0.6 0.4 0.2 0 –75 –50 –25 75 100 125 150 TEMPERATURE (°C) 3071 ...

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LT3071 typicAl perFormAnce chArActeristics Current Limit vs V – OUT 3.3V BIAS T = 25° 1.8V OUT 1.2V OUT V = 0.8V OUT ...

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Bias Voltage Line Regulation 400 V = 3.25V TO 3.6V BIAS V = 2.1V 300 1.8V OUT I = 10mA 200 OUT 100 0 –100 –200 –300 –400 –75 –50 – ...

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LT3071 typicAl perFormAnce chArActeristics Bias Voltage Line Transient Response V OUT 10mV/DIV V BIAS 200mV/DIV 3071 G43 V = 1.3V 20µs/DIV 2.5V BIAS OUT OUT C = 16.9µF OUT Transient Load ...

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Functions VIOC (Pin 1): Voltage for In-to-Out Control. The IC in- corporates a unique tracking function to control a buck regulator powering the LT3071’s input. The VIOC pin is the output of this tracking function that drives the buck regulator to maintain the LT3071’s input voltage at V 300mV. This function maximizes efficiency and minimizes power dissipation. See the Applications Information sec- tion for more information on proper control of the buck regulator. PWRGD (Pin 2): Power Good. The PWRGD pin is an open- drain NMOS output that actively pulls low if any one of these fault modes is detected: • less than 90 OUT OUT(NOMINAL) edge OUT • V drops below 85 OUT OUT(NOMINAL) 25µs. • ...

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LT3071 pin Functions SENSE (Pin 19): Kelvin Sense for OUT . The SENSE pin is the inverting input to the error amplifier. Optimum regulation is obtained when the SENSE pin is connected to the OUT pins of the regulator. In critical applications, the resistance ( PCB traces between the regulator and the load cause P small voltage drops, creating a load regulation error at the point of load. Connecting the SENSE pin at the load instead of directly to OUT eliminates this voltage error. Figure 1 illustrates this Kelvin-Sense connection method. Note that the voltage drop across the external PCB traces adds to the dropout voltage of the regulator. The SENSE pin input bias current depends on the selected output voltage. SENSE pin input current varies from 50µA typically 300µA typically 1.8V. OUT I (Pin 21): Output Current Monitor. The I MON sources a current typically equal to I per amp of output current. ...

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DiAgrAm UVLO AND BIAS 27 THERMAL SHUTDOWN IN 5-8 REF/BYP – VIOC V 1 OUT(NOM) + GND 4,9-14,20,26,29 V BIAS 100k MARGSEL OR MARGTOL 100k + I SENSE – + EAMP ...

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LT3071 ApplicAtions inFormAtion Introduction Current generation FPGA and ASIC processors place stringent demands on the power supplies that power the core, I/O and transceiver channels. These microprocessors may cycle load current from near zero to amps in tens of nanoseconds. Output voltage specifications, especially in the 1V range, require tight tolerances including transient response as part of the requirement. Some ASIC processors require only a single output voltage from which the core and I/O circuitry operate. Some high performance FPGA processors require separate power supply voltages for the processor core, the I/O, and the transceivers. Often, these supply voltages must be low noise and high bandwidth to achieve the lowest bit-error rates. These requirements mandate the need for very accurate, low noise, high cur- rent, very high speed regulator circuits that operate at low input and output voltages. The LT3071 is a low voltage, UltraFast transient response linear regulator. The device supplies output current with a typical dropout voltage of 85mV. A 0.01µF reference bypass capacitor decreases output voltage noise to 25µV (BW = 10Hz to 100kHz). The LT3071’s high RMS bandwidth provides UltraFast transient response using low ESR ceramic output capacitors (15µF minimum), saving bulk capacitance, PCB area and cost. The LT3071’s features permit state-of-the-art linear regula- tor performance. The LT3071 is ideal for high performance FPGAs, microprocessors, sensitive communication sup- plies, and high current logic applications that also operate ...

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ApplicAtions inFormAtion FPGA and ASIC processors are sufficient to stabilize the system (see Stability and Output Capacitance section). This regulator design provides ample bandwidth and responds to transient load changes in a few hundred nanoseconds versus regulators that respond in many microseconds. The LT3071 also incorporates precision current limiting, enable/disable control of output voltage and integrated overvoltage and thermal shutdown protection. The LT3071’s unique design combines the benefits of low dropout voltage, high functional integration, precision performance and UltraFast transient response, as well as providing significant cost savings on the output capacitance needed in fast load transient applications. As lower voltage applications become increasingly preva- lent with higher frequency switching power supplies, the ...

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LT3071 ApplicAtions inFormAtion The REF/BYP pin must not be DC loaded by anything except for applications that parallel other LT3071 regulators for higher output currents. Consult the Applications Section on Paralleling for further details. Output Voltage Margining The LT3071’s analog margining pin, MARGA, provides a continuous output voltage adjustment range of ±10%. It margins V by adjusting the internal 600mV reference OUT voltage up and down. The MARGA pin’s typical input impedance is 190kΩ between MARGA and the internal V node. Driving MARGA with 600mV to 1.2V provides REF 0% to 10% of adjustment. Driving MARGA with 600mV to 0V provides 0% to –10% of adjustment. If unused, allow MARGA to float or bypass this pin with a 1nF capacitor to GND. Note that the analog margining function does not adjust the PWRGD threshold. Therefore, negative analog margining may trip the PWRGD comparator and toggle the PWRGD flag. Enable Function—Turning On and Off ...

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ApplicAtions inFormAtion SWITCHING REGULATOR + REF – PWRGD—Power Good PWRGD pin is an open-drain NMOS digital output that actively pulls low if any one of these fault modes is de- tected: • less than 90 OUT OUT(NOMINAL) edge OUT • V drops below 85 OUT OUT(NOMINAL) 25µs. • less than its undervoltage lockout threshold. BIAS • The OUT-to-IN reverse-current detector activates. • Junction temperature exceeds 145°C typically.* *The junction temperature detector is an early warning indicator that trips approximately 20°C before thermal shutdown engages. Stability and Output ...

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LT3071 ApplicAtions inFormAtion Typical 0603 or 0805 case-size capacitors have an ESL of ~800pH and PCB mounting can contribute up to ~200pH. Thus, it becomes necessary to reduce the parasitic inductance by using a parallel capacitor combination. A suitable methodology must control this paralleling as capacitors with the same self-resonant frequency, f form a tank circuit that can induce ringing of their own accord. Small amounts of ESR (5mΩ to 20mΩ) have some benefit in dampening the resonant loop, but higher ESRs degrade the capacitor response to transient load steps with rise/fall times less than 1µs. The most area efficient parallel capacitor combination is a graduated 4/2/1 scale the same case size. Under these conditions, the R individual ESLs are relatively uniform, and the resonance peaks are deconstructively spread beyond the regulator bandwidth. The recommended parallel combination that approximates 15µF is 10µF + 4.7µF + 2.2µF . Capacitors with case sizes larger than 0805 have higher ESL and lower ESR (<5mΩ). ...

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ApplicAtions inFormAtion 20 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10µF 0 X5R –20 –40 –60 Y5V –80 –100 BIAS VOLTAGE (V) Figure 4. Ceramic Capacitor DC Bias Characteristics 40 BOTH CAPACITORS ARE ...

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LT3071 ApplicAtions inFormAtion the farther the wires are placed apart from each other, the more inductance will be reduced 50% reduction when placed a few inches apart. Splitting the wires basi- cally connects two equal inductors in parallel. However, when placed in close proximity from each other, mutual inductance is added to the overall self inductance of the wires. The most effective way to reduce overall inductance is to place the forward and return-current conductors (the wire for the input and the wire for the return ground) in very close proximity. Two 18-AWG wires separated by 0.05 inch reduce the overall self inductance to about one- fourth of a single isolated wire. If the LT3071 is powered by a battery mounted in close proximity with ground and power planes on the same circuit board, a 47µF input capacitor is sufficient for stability. However, if the LT3071 is powered by a distant supply, use a low ESR, large value input capacitor on the order of 330µ power supply output impedance varies, the minimum input capacitance needed for application stability also varies. Bias ...

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ApplicAtions inFormAtion With a high input voltage, a problem can occur where the removal of an output short will not allow the output volt- age to recover. Other regulators with current limit foldback also exhibit this phenomenon not unique to the LT3071. The load line for such a load may intersect the output current curve at two points: normal operation and the SOA restricted load current settings. A common situ- ation is immediately after the removal of a short circuit, but with a static load ≥ 1A. In this situation, removal of the load or reduction <1A will clear this condition OUT and allow V to return to normal regulation. OUT Reverse Voltage The LT3071 incorporates a circuit that detects if V creases below V . This reverse-voltage detector has OUT a typical threshold of about (V – threshold is exceeded, this detector circuit turns off the drive to the internal NMOS pass transistor, thereby turning off the output. The output pulls low with the load current discharging the output capacitance. This circuit’s intent is to limit and prevent back-feed current from OUT the input voltage collapses due to a fault or overload condition. Thermal ...

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LT3071 ApplicAtions inFormAtion Calculating Junction Temperature Example: Given an output voltage of 0.9V, an input voltage range of 1.2V ± 5%, a BIAS voltage of 2.5V, a maximum out- put current of 4A and a maximum ambient temperature of 50°C, what will the maximum junction temperature be? The power dissipated by the device equals: I • (V – OUT(MAX) IN(MAX) OUT + I • V GND BIAS where OUT(MAX 1.26V IN(MAX 4A 2.5V) = 6.91mA BIAS OUT BIAS 4A 2.5V) = 0.87mA ...

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ApplicAtions inFormAtion Quieting the Noise The LT3071 offers numerous noise performance advan- tages. Each LDO has several sources of noise. An LDO’s most critical noise source is the reference, followed by the LDO error amplifier. Traditional low noise regulators buffer the voltage reference out to an external pin (usually through a large value resistor) to allow for bypassing and noise reduction of reference noise. The LT3071 deviates from the traditional voltage reference by generating a low voltage V from a reference current into an inter- REF nal resistor ≅19k. This intermediate impedance node (REF/BYP) facilitates external filtering directly. A 10nF filter V BIAS 2. 1.5V 330µF ...

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LT3071 typicAl ApplicAtions V BIAS 3.3V 47µ 0.1µF PGOOD RUN PV IN SGND PLLLPF LTC3415EUHF NC CLKOUT PHMODE NC CLKIN MODE PGND PGND PGND PGND NOTES: LTC3415 SWITCHER, 2MHz INTERNAL OSCILLATOR LTC3415 ...

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ApplicAtions V BIAS 3.3V 47µ 0.1µF PGOOD RUN SGND PLLLPF LTC3415EUHF NC CLKOUT PHMODE NC CLKIN MODE PGND PGND PGND PGND PGND NOTES: LTC3415 SWITCHER, 2MHz INTERNAL ...

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LT3071 typicAl ApplicAtions SW1 CLKIN1 CLKOUT1 CLKIN2 CLKOUT2 V V IN1 OUT1 10µF SV MGN1 IN1 RUN1 FB1 PLLLPF1 ITH1 MODE1 ITHM1 PHMODE1 BSEL1 TRACK1 PGOOD1 LTM4616 V V IN2 OUT2 SV ...

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Description 4.50 0.05 3.10 0.05 2.50 REF 2.65 0.05 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 TOP MARK (NOTE 6) 5.00 0.10 (2 SIDES) NOTE: ...

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LT3071 typicAl ApplicAtion V BIAS 2. 1.5V 330µF 1nF relAteD pArts PART DESCRIPTION LT1764/LT1764A 3A, Fast Transient Response, Low Noise LDO LT1963/LT1963A 1.5A Low Noise, Fast Transient Response LDO LT1965 1.1A, Low Noise, Low Dropout Linear Regulator LT3021 500mA, Low Voltage, VLDO™ Linear Regulator LT3080/LT3080-1 1.1A, Parallelable, Low Noise, Low Dropout Linear Regulator LT3085 500mA, Parallelable, Low Noise, Low Dropout Linear Regulator LTC3025-1/LTC3025-2/ 500mA Micropower VLDO Linear Regulator LTC3025-3/LTC3025-4 in 2mm × 2mm DFN LTC3026 1.5A, Low Input Voltage VLDO Regulator LT3070 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator ...