STM8S105C4B3 STMICROELECTRONICS [STMicroelectronics], STM8S105C4B3 Datasheet
STM8S105C4B3
Related parts for STM8S105C4B3
STM8S105C4B3 Summary of contents
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Access line, 16 MHz STM8S 8-bit MCU Kbytes Flash, integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C LQFP48 7x7 LQFP44 10x10 VFQFPN32 5x5 UFQFPN32 5x5 Features Core • 16 MHz advanced STM8 core with Harvard architecture and 3-stage ...
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Contents Contents 1 Introduction ..............................................................................................................8 2 Description ...............................................................................................................9 3 Block diagram ........................................................................................................11 4 Product overview ...................................................................................................12 4.1 Central processing unit STM8 .....................................................................................12 4.2 Single wire interface module (SWIM) and debug module (DM) ..................................12 4.3 Interrupt controller .......................................................................................................13 4.4 Flash program ...
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STM8S105xx 10.1.3 Typical curves ....................................................................................58 10.1.4 Typical current consumption ..............................................................58 10.1.5 Loading capacitor ...............................................................................59 10.1.6 Pin input voltage .................................................................................59 10.2 Absolute maximum ratings ........................................................................................59 10.3 Operating conditions ..................................................................................................61 10.3.1 VCAP external capacitor ....................................................................64 10.3.2 Supply current characteristics ............................................................64 10.3.3 External ...
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List of tables List of tables Table 1. Device summary .........................................................................................................................1 Table 2. STM8S105xx access line features .............................................................................................9 Table 3. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................15 Table 4. TIM timer features ...................................................................................................................17 Table 5. Legend/abbreviations ..............................................................................................................21 Table ...
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STM8S105xx Table 48. EMS data ..............................................................................................................................103 Table 49. EMI data ...............................................................................................................................103 Table 50. ESD absolute maximum ratings ...........................................................................................104 Table 51. Electrical sensitivities ...........................................................................................................104 Table 52. 48-pin low profile quad flat package mechanical data .........................................................106 Table 53. 44-pin low profile quad ...
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List of figures List of figures Figure 1. STM8S105xx access line block diagram ................................................................................11 Figure 2. Flash memory organisation ....................................................................................................14 Figure 3. LQFP 48-pin pinout .................................................................................................................22 Figure 4. LQFP 44-pin pinout .................................................................................................................23 Figure 5. LQFP/VFQFPN/UFQFPN 32-pin pinout ................................................................................24 Figure 6. ...
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STM8S105xx Figure 48. 44-pin low profile quad flat package ...................................................................................108 Figure 49. 32-pin low profile quad flat package ( ........................................................................109 Figure 50. 32-lead very thin fine pitch quad flat no-lead package ( ............................................112 Figure 51. 32-lead ...
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Introduction 1 Introduction This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information. • For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference ...
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STM8S105xx 2 Description The STM8S105xx access line 8-bit microcontrollers offer from Kbytes Flash program memory, plus integrated true data EEPROM. They are referred to as medium-density devices in the STM8S microcontroller family reference manual (RM0016). All devices ...
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Description Device STM8S105C6 Peripheral set Advanced control timer (TIM1), General-purpose timers (TIM2 and TIM3), Basic timer (TIM4) SPI, I Window WDG, Independent WDG, ADC 10/127 STM8S105C4 STM8S105S6 DocID14771 Rev 9 STM8S105xx STM8S105S4 STM8S105K6 STM8S105K4 2 C, UART, ...
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STM8S105xx 3 Block diagram Figure 1: STM8S105xx access line block diagram Reset POR Single wire debug interf. Master/slave autosynchro LIN master SPI emul. 400 Kbit/s 8 Mbit channels 1/2/4 kHz beep Reset block Clock controller Reset Detector ...
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Product overview 4 Product overview The following section intends to give an overview of the basic features of the device functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing ...
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STM8S105xx SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms. Debug module The non-intrusive debugging module ...
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Product overview The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the ...
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STM8S105xx - 16 MHz high-speed internal RC oscillator (HSI) - 128 kHz low-speed internal RC (LSI) • Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can ...
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Product overview 4.7 Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled ...
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STM8S105xx 4.10 TIM1 - 16-bit advanced control timer This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, ...
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Product overview Timer Counter Prescaler size (bits) TIM4 8 Any power of 2 from 1 to 128 4.13 Analog-to-digital converter (ADC1) The STM8 family products contain a 10-bit successive approximation A/D converter (ADC1) with external multiplexed input ...
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STM8S105xx Asynchronous communication (UART mode) • Full duplex communication - NRZ standard format (mark/space) • Programmable transmit and receive baud rates Mbit/s (f following any standard baud rate regardless of the input frequency • Separate enable bits ...
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Product overview - Start and stop generation • I²C slave features: - Programmable I2C address detection - Stop bit detection • Generation and detection of 7-bit/10-bit addressing and general call • Supports different communication speeds: - Standard speed (up to ...
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STM8S105xx 5 Pinout and pin description Type Level Output speed Port and control configuration Reset state HS (T) [] Table 5: Legend/abbreviations I= Input Output Power supply CM = CMOS Input Output HS = High sink ...
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Pinout and pin description 5.1 STM8S105 pinouts and pin description [TIM3_CH1] TIM2_CH3/PA3 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode alternate function remapping option (If the same alternate function ...
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STM8S105xx 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication ...
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Pinout and pin description 1. (HS) high sink capability alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 24/127 Figure 5: LQFP/VFQFPN/UFQFPN 32-pin ...
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STM8S105xx ADC_ETR/TIM2_CH2/PD3(HS) 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a ...
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Pinout and pin description Pin number Pin name LQFP48 LQFP44 LQFP32/ SDIP32 VFQFPN32/ UFQFPN32 PA3/ TIM2 _CH3 [TIM3 _CH1 PA4 PA5 PA6 - - ...
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STM8S105xx Pin number Pin name LQFP48 LQFP44 LQFP32/ SDIP32 VFQFPN32/ UFQFPN32 PE6/ AIN9 PE5/SPI_ NSS PC1/ TIM1_ CH1 ...
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Pinout and pin description Pin number Pin name LQFP48 LQFP44 LQFP32/ SDIP32 VFQFPN32/ UFQFPN32 PD0/ TIM3_ CH2 [TIM1_ BKIN] [CLK_ CCO PD1/ SWIM PD2/ TIM3_ CH1 [TIM2_ CH3] ...
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STM8S105xx 6 Memory and register map 6.1 Memory map The following table lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case. Figure 7: Memory map 0x00 0000 ...
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Memory and register map Table 7: Flash, Data EEPROM and RAM boundary addresses Memory area Flash program memory RAM Data EEPROM 6.2 Register map 6.2.1 I/O port hardware register map Address Block 0x00 5000 Port A 0x00 5001 0x00 5002 ...
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STM8S105xx Address Block 0x00 500A Port C 0x00 500B 0x00 500C 0x00 500D 0x00 500E 0x00 500F Port D 0x00 5010 0x00 5011 0x00 5012 0x00 5013 0x00 5014 Port E 0x00 5015 0x00 5016 0x00 5017 0x00 5018 0x00 ...
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Memory and register map Address Block 0x00 501D 0x00 501E Port G 0x00 501F 0x00 5020 0x00 5021 0x00 5022 0x00 5023 Port H 0x00 5024 0x00 5025 0x00 5026 0x00 5027 0x00 5028 Port I 0x00 5029 0x00 502A ...
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STM8S105xx 6.2.2 General hardware register map Address Block 0x00 Reserved area (10 bytes) 5050 to 0x00 5059 0x00 Flash 505A 0x00 505B 0x00 505C 0x00 505D 0x00 505E 0x00 505F 0x00 Reserved area (2 bytes) 5060 to 0x00 5061 0x00 ...
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Memory and register map Address Block 0x00 Reserved area (59 bytes) 5065 to 0x00 509F 0x00 ITC - 50A0 EXTI 0x00 50A1 0x00 Reserved area (17 bytes) 50A2 to 0x00 50B2 0x00 RST 50B3 0x00 Reserved area (12 bytes) 50B4 ...
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STM8S105xx Address Block 0x00 50C6 0x00 50C7 0x00 50C8 0x00 50C9 0x00 50CA 0x00 50CB 0x00 50CC 0x00 50CD 0x00 Reserved area (3 bytes) 50CE to 0x00 50D0 0x00 WWDG 50D1 0x00 50D2 0x00 Reserved area (13 bytes) 50D3 to ...
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Memory and register map Address Block 0x00 IWDG 50E0 0x00 50E1 0x00 50E2 0x00 Reserved area (13 bytes) 50E3 to 0x00 50EF 0x00 AWU 50F0 0x00 50F1 0x00 50F2 0x00 BEEP 50F3 0x00 Reserved area (12 bytes) 50F4 to 0x00 ...
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STM8S105xx Address Block 00 5205h 00 5206h 00 5207h 00 5208h Reserved area (8 bytes 520Fh 2 00 5210h 5211h 00 5212h 00 5213h 00 5214h 00 5215h 00 5216h 00 5217h 00 5218h 00 ...
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Memory and register map Address Block 00 521Eh 00 521Fh Reserved area (17 bytes 522Fh 0x00 Reserved area (6 bytes) 5230 to 0x00 523F 0x00 UART2 5240 0x00 5241 0x00 5242 0x00 5243 0x00 5244 0x00 5245 0x00 ...
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STM8S105xx Address Block 0x00 524A 0x00 524B 0x00 Reserved area (4 bytes) 524C to 0x00 524F 0x00 TIM1 5250 0x00 5251 0x00 5252 0x00 5253 0x00 5254 0x00 5255 0x00 5256 0x00 5257 0x00 5258 0x00 5259 Register label Register ...
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Memory and register map Address Block 0x00 525A 0x00 525B 0x00 525C 0x00 525D 0x00 525E 0x00 525F 0x00 5260 0x00 5261 0x00 5262 0x00 5263 0x00 5264 0x00 5265 0x00 5266 40/127 Register label Register name TIM1_CCMR3 TIM1 capture/ ...
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STM8S105xx Address Block 0x00 5267 0x00 5268 0x00 5269 0x00 526A 0x00 526B 0x00 526C 0x00 526D 0x00 526E 0x00 526F 0x00 Reserved area (147 bytes) 5270 to 0x00 52FF 0x00 TIM2 5300 0x00 5301 0x00 5302 Register label Register ...
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Memory and register map Address Block 0x00 5303 0x00 5304 0x00 5305 0x00 5306 0x00 5307 0x00 5308 0x00 5309 0x00 530A 0x00 530B 0x00 530C 0x00 530D 0x00 530E 0x00 530F 42/127 Register label Register name TIM2_SR2 TIM2 status ...
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STM8S105xx Address Block 0x00 5310 0x00 5311 0x00 5312 0x00 5313 0x00 5314 0x00 Reserved area (11 bytes) 5315 to 0x00 531F 0x00 TIM3 5320 0x00 5321 0x00 5322 0x00 5323 0x00 5324 0x00 5325 0x00 5326 Register label Register ...
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Memory and register map Address Block 0x00 5327 0x00 5328 0x00 5329 0x00 532A 0x00 532B 0x00 532C 0x00 532D 0x00 532E 0x00 532F 0x00 5330 0x00 Reserved area (15 bytes) 5331 to 0x00 533F 0x00 TIM4 5340 0x00 5341 ...
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STM8S105xx Address Block 0x00 5342 0x00 5343 0x00 5344 0x00 5345 0x00 5346 0x00 Reserved area (153 bytes) 5347 to 0x00 53DF 0x00 ADC1 53E0 to 0x00 53F3 0x00 Reserved area (12 bytes) 53F4 to 0x00 53FF 0x00 ADC1 5400 ...
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Memory and register map Address Block 0x00 5404 0x00 5405 0x00 5406 0x00 5407 0x00 5408 0x00 5409 0x00 540A 0x00 540B 0x00 540C 0x00 540D 0x00 540E 0x00 540F 0x00 Reserved area (1008 bytes) 5410 to 46/127 Register label ...
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STM8S105xx Address Block 0x00 57FF 6.2.3 CPU/SWIM/debug module/interrupt controller registers Table 10: CPU/SWIM/debug module/interrupt controller registers Address Block 0x00 7F00 CPU 0x00 7F01 0x00 7F02 0x00 7F03 0x00 7F04 0x00 7F05 0x00 7F06 0x00 7F07 0x00 7F08 0x00 7F09 0x00 ...
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Memory and register map Address Block 0x00 7F70 ITC - SPR 0x00 7F71 0x00 7F72 0x00 7F73 0x00 7F74 0x00 7F75 0x00 7F76 0x00 7F77 0x00 7F78 Reserved area (2 bytes) to 0x00 7F79 0x00 7F80 SWIM 0x00 7F81 Reserved ...
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STM8S105xx Address Block 0x00 7F97 0x00 7F98 0x00 7F99 0x00 7F9A 0x00 Reserved area (5 bytes) 7F9B to 0x00 7F9F (1) Accessible by debug module only Register label Register name DM_CR2 DM debug module control register 2 DM_CSR1 DM debug ...
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Interrupt vector mapping 7 Interrupt vector mapping IRQ Source no. block RESET TRAP 0 TLI 1 AWU 2 CLK 3 EXTI0 4 EXTI1 5 EXTI2 6 EXTI3 7 EXTI4 SPI 11 TIM1 12 TIM1 13 TIM 14 ...
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STM8S105xx IRQ Source no. block 15 TIM3 16 TIM3 UART2 21 UART2 22 ADC1 23 TIM 24 Flash Reserved (1) Except PA1 Description Wakeup from halt mode Update/ overflow - Capture/ compare - ...
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Option bytes 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each ...
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STM8S105xx Addr. Option Option Option bits name byte no. 7 NOPT6 0x480C Reserved OPT7 0x480D Reserved Reserved NOPT7 0x480E Reserved OPTBL 0x487E Bootloader BL[7:0] NOPTBL 0x487F NBL[7:0] Option byte no. OPT0 OPT1 OPT2 OPT3 Table 13: ...
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Option bytes Option byte no. OPT4 OPT5 54/127 Description LSI_EN:Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI clock is available as CPU clock source IWDG_HW: Independent watchdog 0: IWDG Independent watchdog ...
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STM8S105xx Option byte no. OPT6 OPT7 OPTBL Table 14: Description of alternate function remapping bits [7:0] of OPT2 Option byte no. OPT2 Description Reserved Reserved BL[7:0] Bootloader option byte For STM8S products, this option is checked by the boot ROM ...
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Option bytes Option byte no. (1) Do not use more than one remapping option in the same port. (2) Refer to pinout description. 56/127 (1) Description 0: AFR2 remapping option inactive: Default alternate function 1: Port D0 alternate function = ...
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STM8S105xx 9 Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. ...
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Electrical characteristics 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...
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STM8S105xx 10.1.5 Loading capacitor The loading conditions used for pin parameter measurement are shown in the following figure. 10.1.6 Pin input voltage The input voltage measurement on a pin of the device is described in the following figure. 10.2 Absolute ...
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Electrical characteristics Symbol Ratings Input voltage on any other pin |V - Variations between different power pins DDx Variations between all the different ground pins SSx SS V Electrostatic discharge voltage ESD (1) ...
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STM8S105xx Symbol Ratings (4) (5) I INJ(PIN) (4) ΣI INJ(PIN) (1) Data based on characterization results, not tested in production. (2) All power (V DD connected to the external supply. (3) I/O pins used simultaneously for high current source/sink must ...
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Electrical characteristics Symbol f CPU DD_IO VCAP ( (1) Care should be taken when selecting the capacitor, due to its tolerance, as well as its dependency on temperature, DC bias ...
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STM8S105xx (2) To calculate P characteristics ) with the value for T given in Thermal (3) Refer to Thermal ( given by the test limit. Above this value the product behavior is not guaranteed. Jmax Functionality not guaranteed ...
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Electrical characteristics 10.3.1 VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor C V pin specified in the Operating conditions section. Care should be taken to limit CAP EXT the series inductance to ...
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STM8S105xx Symbol Parameter I DD(RUN) Supply current in run mode, code executed fromFlash (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. Table 22: Total current consumption with code execution ...
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Electrical characteristics Symbol Parameter mode, code executed from RAM Supply current in run mode, code executed from Flash 66/127 Conditions HSE user ext. clock (16 MHz) HSI RC osc. (16 MHz /128 HSE user ext. clock CPU ...
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STM8S105xx Symbol Parameter (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. 10.3.2.2 Total current consumption in wait mode Table 23: Total current consumption in wait mode at V Symbol ...
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Electrical characteristics Table 24: Total current consumption in wait mode at V Symbol Parameter I Supply DD(WFI) current in wait mode (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. ...
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STM8S105xx Symbol Parameter (1) Data based on characterization results, not tested in production (2) Configured by the REGAH bit in the CLK_ICKR register. (3) Configured by the AHALT bit in the FLASH_CR1 register. Table 26: Total current consumption in active ...
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Electrical characteristics Symbol Parameter (1) Data based on characterization results, not tested in production. (2) Configured by the REGAH bit in the CLK_ICKR register. (3) Configured by the AHALT bit in the FLASH_CR1 register. 10.3.2.4 Total current consumption in halt ...
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STM8S105xx Table 28: Total current consumption in halt mode at V Symbol Parameter I Supply current DD(H) in halt mode (1) Data based on characterization results, not tested in production. 10.3.2.5 Low power mode wakeup times Symbol Parameter Wakeup time ...
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Electrical characteristics (4) Configured by the REGAH bit in the CLK_ICKR register. (5) Configured by the AHALT bit in the FLASH_CR1 register. (6) Plus 1 LSI clock depending on synchronization. 10.3.2.6 Total current consumption and timing in forced reset state ...
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STM8S105xx Symbol Parameter DD ADC1 supply current when converting DD(ADC1) (1) Data based on a differential I counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production. (2) ...
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Electrical characteristics Figure 14: Typ. I Figure 15: Typ. I 74/127 vs. f HSE user external clock, V DD(RUN) CPU , vs. V HSI RC osc, f DD(RUN DocID14771 Rev 9 STM8S105xx = ...
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STM8S105xx Figure 16: Typ. I Figure 17: Typ. I vs. V HSE user external clock, f DD(WFI vs HSE user external clock V DD(WFI) CPU DocID14771 Rev 9 Electrical characteristics = 16 MHz CPU = 5 ...
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Electrical characteristics Figure 18: Typ. I 10.3.3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for V Table 32: HSE user external clock characteristics Symbol Parameter f User external clock source HSE_ext frequency ...
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STM8S105xx V HSEH V HSEL HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external ...
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Electrical characteristics ( the start-up time measured from the moment it is enabled (by software stabilized 16 SU(HSE) MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly ...
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STM8S105xx Symbol Parameter Accuracy of HSI oscillator (factory calibrated) t HSI oscillator su(HSI) wakeup time including calibration I HSI oscillator power DD(HSI) consumption (1) Refer to application note. (2) Guaranteed by design, not tested in production. (3) Data based on ...
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Electrical characteristics Figure 22: Typical HSI accuracy vs V Low speed internal RC oscillator (LSI) Subject to general operating conditions for V Symbol Parameter f Frequency LSI t LSI oscillator wakeup time su(LSI) I LSI oscillator power consumption DD(LSI) (1) ...
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STM8S105xx Figure 23: Typical LSI accuracy vs V 10.3.5 Memory characteristics RAM and hardware registers Symbol Parameter V Data retention mode RM (1) Minimum supply voltage without losing data stored in RAM (in halt mode or under reset ...
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Electrical characteristics Symbol Parameter Fast programming time for 1 block (128 bytes) t Erase time for 1 block (128 bytes) erase N Erase/write cycles RW memory) Erase/write cycles(data memory) t Data retention (program memory) RET after 10k erase/write cycles at ...
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STM8S105xx Symbol Parameter V Input high level IH voltage V Hysteresis hys R Pull-up resistor Rise and fall R F time( Input leakage lkg current, analog and digital I Analog input ...
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Electrical characteristics Figure 25: Typical pull-up resistance vs V Figure 26: Typical pull-up current The pull- pure resistor (slope goes through 0). Symbol Parameter V Output low level with four pins OL sunk 84/127 Table ...
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STM8S105xx Symbol Parameter Output low level with eight pins sunk V Output high level with four OH pins sourced Output high level with eight pins sourced (1) Data based on characterization results, not tested in production Table 40: Output driving ...
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Electrical characteristics Symbol Parameter Output high level with eight pins sourced Output high level with four pins sourced (1) Data based on characterization results, not tested in production 10.3.7 Typical output level curves The following figures show typical output level ...
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STM8S105xx Figure 29: Typ. V Figure 28: Typ 3.3 V (standard ports (true open drain ports DocID14771 Rev 9 Electrical characteristics 87/127 ...
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Electrical characteristics Figure 30: Typ. V 88/127 @ V = 3.3 V (true open drain ports Figure 31: Typ (high sink ports DocID14771 Rev 9 STM8S105xx ...
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STM8S105xx Figure 32: Typ Figure 33: Typ DocID14771 Rev 9 Electrical characteristics = 3.3 V (high sink ports (standard ports) DD 89/127 ...
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Electrical characteristics Figure 34: Typ. V Figure 35: Typ. V 90/127 - 3.3 V (standard ports (high sink ports DocID14771 Rev 9 STM8S105xx ...
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STM8S105xx Figure 36: Typ. V 10.3.8 Reset pin characteristics Subject to general operating conditions for V Symbol Parameter V NRST input low IL(NRST) (1) level voltage V NRST input high IH(NRST) level voltage V NRST output low OL(NRST) level voltage ...
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Electrical characteristics Figure 37: Typical NRST V Figure 38: Typical NRST pull-up resistance vs V 92/127 and temperatures DocID14771 Rev 9 STM8S105xx @ 4 temperatures ...
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STM8S105xx Figure 39: Typical NRST pull-up current vs V The reset network shown inthe following figure protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the V in the ...
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Electrical characteristics Symbol Parameter f 1 SPI clock SCK frequency t c(SCK) t SPI clock rise r(SCK) and fall time t f(SCK) (1) t NSS setup time su(NSS) (1) t NSS hold time h(NSS) (1) t SCK high and w(SCKH) ...
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STM8S105xx Symbol Parameter (1) t Data output h(SO) hold time (1) t h(MO) (1) Values based on design simulation and/or characterization results, and not tested in production. (2) Min time is for the minimum time to drive the output and ...
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Electrical characteristics Figure 42: SPI timing diagram - slave mode and CPHA = 1 NSS input t SU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 t a(SO) MISO OUT P UT MOSI I NPUT 1. Measurement points are made at CMOS levels: 0.3 ...
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STM8S105xx 2 10.3. interface characteristics Symbol Parameter t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time h(SDA) t r(SDA) SDA and SCL rise time t ...
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Electrical characteristics Figure 44: Typical application with I I²C bus SDA t f(SDA) SCL t w(SCKH) 1. Measurement points are made at CMOS levels: 0 10.3.11 10-bit ADC characteristics Subject to general operating conditions for V Symbol Parameter ...
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STM8S105xx Symbol Parameter (2) t Sampling time S t Wakeup time from standby STAB t Total conversion time CONV (including sampling time, 10-bit resolution) (1) Data guaranteed by design, not tested in production.. (2) During the sample time the input ...
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Electrical characteristics Symbol Parameter |E | Differential linearity error Integral linearity error L (1) Data based on characterisation results for LQFP80 device with V in production. (2) ADC accuracy vs. negative injection current: Injecting negative current on ...
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STM8S105xx Symbol Parameter |E | Integral linearity error L (1) Data based on characterisation results for LQFP80 device with V in production. (2) ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should ...
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Electrical characteristics E = Integral linearity error: maximum deviation between any actual transition and the end L point correlation line. V AIN 10.3.12 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 10.3.12.1 Functional EMS (electromagnetic ...
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STM8S105xx Symbol Parameter V Voltage limits to be FESD applied on any I/O pin to induce a functional disturbance V Fast transient voltage EFTB burst limits to be applied through 100 and V SS functional disturbance (1) ...
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Electrical characteristics 10.3.12.4 Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to ...
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STM8S105xx (1) Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the ...
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Package characteristics 11 Package characteristics 11.1 Ecopack packages To meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK grade definitions and product status are available at www.st.com. ECOPACK ...
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STM8S105xx Dim. mm Min c 0.090 D 8.800 D1 6.800 D3 E 8.800 E1 6.800 0.450 L1 k 0.0° ccc (1) Values in inches are converted from mm and rounded to 4 decimal digits inches Typ Max ...
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Package characteristics 11.2.2 44-pin LQFP package mechanical data Pin 1 identification Table 53: 44-pin low profile quad flat package mechanical data Dim. mm Min A A1 0.050 A2 1.350 b 0.300 c 0.090 D 11.800 D1 9.800 ...
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STM8S105xx Dim. mm Min E1 9.800 0.450 L1 k 0.0° ccc (1) Values in inches are converted from mm and rounded to 4 decimal digits 11.2.3 32-pin LQFP package mechanical data Pin 1 ...
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Package characteristics Table 54: 32-pin low profile quad flat package mechanical data Dim. mm Min A A1 0.050 A2 1.350 b 0.300 c 0.090 D 8.800 D1 6.800 D3 E 8.800 E1 6.800 0.450 L1 k 0.0° ...
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STM8S105xx 11.2.4 32-lead VFQFPN package mechanical data Figure 50: 32-lead very thin fine pitch quad flat no-lead package ( Note: 1. The exposed pad must be soldered to the PCB recommended to connect it to VSS. ...
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Package characteristics Dim. mm Min D2 3.20 E 4. 0.30 ddd (1) Values in inches are converted from mm and rounded to 4 decimal digits. 11.2.5 32-lead UFQFPN package mechanical data Figure 51: 32-lead ultra thin ...
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STM8S105xx Table 56: 32-lead ultra thin fine pitch quad flat no-lead package mechanical data Dim. mm Min A 0. 0.18 D 4.85 D2 3.20 E 4. 0.30 ddd (1) Values in inches ...
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Package characteristics 11.2.6 SDIP32 package mechanical data Table 57: 32-lead shrink plastic DIP (400 ml) package mechanical data Dim. mm Min A 3.556 A1 0.508 A2 3.048 B 0.356 B1 0.762 C 0.203 D 27.430 E 9.906 E1 7.620 114/127 ...
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STM8S105xx Dim. mm Min 2.540 (1) Values in inches are converted from mm and rounded to 4 decimal digits 11.3 Thermal characteristics The maximum chip junction temperature (T Operating conditions The maximum chip-junction temperature, T the ...
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Package characteristics Symbol Parameter Θ Thermal resistance junction-ambient JA LQFP Θ Thermal resistance junction-ambient JA VQFPN Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in ...
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STM8S105xx 12 Ordering information Figure 53: STM8S105xx access line ordering information scheme Example: Product class Family type S = Standard Sub-family type 105 = access line STM8S105x Pin count pins pins ...
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Ordering information Contact Phone no. Reference FASTROM code Preferable format for programing code is .Hex (.s19 is accepted) If data EEPROM programing is required, a seperate file must be sent with the requested data. Important: See the option byte section ...
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STM8S105xx UBC, bit0 UBC bit1 UBC bit2 UBC bit3 UBC bit4 UBC bit5 UBC bit6 UBC bit7 OPT2 alternate function remapping AFR0 (check only one option) AFR1 (check only one option) AFR2 (check only one option) AFR3 (check only one ...
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Ordering information AFR4 (check only one option) AFR5 (check only one option) AFR6 (check only one option) AFR7 (check only one option) OPT3 watchdog WWDG_HALT (check only one option) WWDG_HW (check only one option) IWDG_HW (check only one option) LSI_EN ...
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STM8S105xx CKAWUSEL (check only one option) EXTCLK (check only one option) OPT5 crystal oscillator stabilization HSECNT (check only one option 2048 HSE cycles [ ] 128 HSE cycles [ ] 8 HSE cycles [ ] 0.5 HSE cycles ...
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STM8 development tools 13 STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, ...
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STM8S105xx 13.2.1 STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes: ST Visual Develop – Full-featured integrated development environment from ST, featuring • Seamless integration of ...
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Revision history 14 Revision history Date Revision 05-Jun-2008 1 23-Jun-2008 2 12-Aug-2008 3 17-Sep-2008 4 05-Feb-2009 5 27-Feb-2009 6 12-May-2009 7 124/127 Table 59: Document revision history Changes Initial release. Corrected number of high sink outputs I/Os ...
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STM8S105xx Date Revision 10-Jun-2009 8 21-Apr-2010 9 Changes Amended name of package VQFPN32 Added Table 5 on page 22 . Updated Auto wakeup counter. Updated pins 25, 30, and 31 in Removed Table 7: Pin-to-pin comparison of pin 7 to ...
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Revision history Date Revision 126/127 Changes Option bytes: added description of STM8L bootloader option bytes to the option byte description table. Added Unique ID Operating conditions: added introductory text; removed low power dissipation condition for T and added ESR and ...
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STM8S105xx Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at ...