ADP5061 AD [Analog Devices], ADP5061 Datasheet
ADP5061
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ADP5061 Summary of contents
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... These digital input/output pins permit combinations of features such as, input current limits, charging enable and disable, charging current limits, and a dedicated interrupt output pin. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ADP5061 ADP5061 SYSTEM ISO_S VIN CBP C3 47µF ...
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... ADP5061 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Typical Application Circuit ............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Recommended Input and Output Capacitances ...................... C-Compatible Interface Timing Specifications ..................... 6 Absolute Maximum Ratings ....................................................... 7 Thermal Resistance ...................................................................... 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ............................................. 9 Temperature Characteristics ..................................................... 11 Typical Waveforms ..................................................................... 13 Theory of Operation ...
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... V > V BAT_SNS TRK_DEAD ms mΩ On battery supplement mode, VINx = 500 mA ISO_B V VTRM[5:0] programming ≥ 4.00 V VTRM[5:0] programming < 4. < rising ISO_S ISO_B SYS ADP5061 = 22 µF, 1 BAT_SNS rising VIN = −40° +115° 4.2 V, ISO_B ...
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... ADP5061 Parameter LDO AND HIGH VOLTAGE BLOCKING Regulated System Voltage Load Regulation High Voltage Blocking FET (LDO FET) On Resistance Maximum Output Current VINx Input Voltage, Good Threshold Rising VINx Falling VINx Input Overvoltage Threshold Hysteresis VINx Transition Timing THERMAL CONTROL Isothermal Charging Temperature ...
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... TRK RCH END DEAD VIN_OK sec min sec ILED V Ω SYS_EN V Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3 V Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3 V Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3 kΩ Applies to DIG_IO1, DIG_IO2, DIG_IO3 2 C. ADP5061 ...
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... ADP5061 RECOMMENDED INPUT AND OUTPUT CAPACITANCES Table 2. Parameter Symbol CAPACITANCES VINx C VIN CBP C BP ISO_Sx C ISO_S ISO_Bx C ISO_B I 2 C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS Table 3. Parameter C-COMPATIBLE INTERFACE 2 Capacitive Load for Each Bus Line SCL Clock Frequency SCL High Time SCL Low Time ...
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... Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, thereby perma- nently shifting the parametric performance of the ADP5061. Exceeding a junction temperature of 175°C for an extended period can result in changes in the silicon devices, potentially causing failure ...
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... I is input output, I/O is input/output ground, and GPIO is factory programmable general-purpose input/output. 2 See the Digital Input and Output Options section for details. DIG_IOx setting defines the initial state of the ADP5061. When the parameter or the mode that is related to each DIG_IOx pin setting is changed (by programming the 3 equivalent I ...
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... SYSTEM OUTPUT CURRENT (A) VSYSTEM[2:0] = 111 (Binary) = 5.0 V 5.4 LOAD = 100mA LOAD = 500mA 5.2 LOAD = 1000mA 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 4.0 4.4 4.8 5.2 5.6 6.0 INPUT VOLTAGE (V) VSYSTEM[2:0] = 111 (Binary) = 5.0 V 700 WEAK 600 CHARGE 500 FAST CHARGE 400 300 200 TRICKLE CHARGE 100 0 2.3 2.8 3.3 3.8 BATTERY VOLTAGE (V) (Binary) = 500 mA, ILIM[3:0] = 1111 (Binary) = 2100 mA ADP5061 1 = 6.0 V, VIN 6.4 6.8 4.3 ...
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... ADP5061 2.7 3.2 BATTERY VOLTAGE (V) Figure 10. Ideal Diode R vs. Battery Voltage 4.0 DEFAULT STARTUP DIS_LDO = HIGH 3.5 DIS_IC1 = HIGH 3.0 2.5 2.0 1.5 1.0 0 INPUT VOLTAGE (V) Figure 11. VINx Current vs. VINx Voltage 3.7 4.2 = 500 mA, VINx Open ISO_S 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3 Figure 13. Charge Profile, ILIM[3:0] = 0110 (Binary) = 500 mA, Battery Rev ...
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... V and VINx = 5 5.0 V and VINx = 6.0 V ISO_S 6.7V IN –25 – AMBIENT TEMPERATURE (° 3.8V TRM V = 4.2V TRM V = 4.5V TRM –25 – AMBIENT TEMPERATURE (°C) Figure 19. Termination Voltage vs. Ambient Temperature ADP5061 110 125 110 125 110 125 ...
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... ADP5061 1 1300mA CHG 1.3 1.2 1.1 1.0 0.9 0 750mA CHG 0.7 0 500mA CHG 0.5 0.4 –40 – AMBIENT TEMPERATURE (°C) Figure 20. Fast Charge CC Mode Current vs. Ambient Temperature 7.00 6.95 6.90 6.85 6.80 –40 –25 – AMBIENT TEMPERATURE (°C) Figure 21. VINx Overvoltage Threshold vs. Ambient Temperature 60 85 110 80 95 110 125 Rev Page ...
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... VIN I ISO_B I VIN Figure 26. VBUS Disconnect V ISO_S I ISO_B I ISO_S Figure 27. Load Transient. I ISO_Sx EN_CHG = High, ILIM[3:0] = 0110 (Binary) = 500 mA V ISO_B I ISO_B Figure 28. Battery Detection Waveform, VSYSTEM[2:0] = 000 (Binary) = 4.3 V, Rev Page ADP5061 Load = 300 mA to 1500 mA to 300 mA, No Battery ...
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... ADP5061 THEORY OF OPERATION SUMMARY OF OPERATION MODES Table 7. Summary of the ADP5061 Operation Modes VINx Mode Name Condition IC Off, Standby Off, Suspend 5 V LDO Mode Off, Isolation 5 V FET On LDO Mode Off, Isolation 5 V FET Off (System Off) LDO Mode, Charger Off ...
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... Fast charge safety timer period • Watchdog safety timer parameters • Weak battery threshold detection • Charge complete threshold • Recharge threshold • Charge enable/disable ADP5061 is chargeable • Battery pack temperature detection and automatic charger shutdown Rev Page ADP5061 ADP5061 can be set ...
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... ADP5061 VIN1 E3 TO USB VBUS OR WALL ADAPTER VIN2 D3 VIN3 + C3 – 6.85V VIN OVERVOLTAGE CBP B3 + 3.9V – VIN GOOD SCL A4 SDA INTERFACE DIG_IO1 AND E4 CONTROL LOGIC DIG_IO2 C4 DIG_IO3 B4 SYS_EN A2 SYS_EN OUTPUT LOGIC ILED A1 ILED OUTPUT LOGIC HIGH VOLTAGE BLOCKING LDO-FET + LDO-FET ...
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... I 100 mA input current limit or I 500 mA input current limit or I 150 mA input current limit or I 900 mA input current limit or I 1500 mA input current limit or I Rev Page ADP5061 2 C programmed 2 C programmed 2 C value from 100 mA ...
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... FET when V ISO_B . The ADP5061 charger monitors the voltage TRM ADP5061 enters a constant voltage ADP5061 reduces charge current gradually as without the voltage at the BAT_SNS pin CHG , a fault condition is assumed and charging stops. TRM CHG , charging stops. No fault condition is ...
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... By default, the charging voltage limit is disabled and it can be enabled from I , charging stops SYS_EN Output again, the t The ADP5061 END END system until the battery is at the minimum required level for guaranteed system start-up. When there are minimum battery voltage and/or minimum battery charge level requirements, the ...
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... FET enters into full conducting mode. When voltage on ISO_Sx rises above ISO_Bx, the isolation FET enters regulating mode or full conduction mode, depending on the Li-Ion cell voltage and the linear charger mode. BATTERY DETECTION , the ADP5061 SD ADP5061 Battery Voltage Level Detection The ADP5061 detect an absent battery ...
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... The ADP5061 in the battery pack with a temperature coefficient curve (beta). Factory programming supports eight beta values covering a range from 3150 to 4400 (see Table 44). ...
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... Normal battery charging occurs at default/programmed levels Battery termination voltage ( reduced by 100 mV from TRM programmed value No battery charging occurs Rev Page Data Sheet ADP5061 identifies a hot or cold battery condition, takes the following actions: continues in LDO mode. Min ...
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... POWER-ON RESET RESET ALL REGISTERS NO IC OFF NO VINOK YES YES NO ENABLE ENABLE CHARGER LDO YES ENABLE CHARGER YES LOW YES BATTERY CHG NO TO CHARGING-MODE Figure 32. Simplified Battery and VIN Connect Flowchart Rev Page LDO MODE NO V BAT_SNS NO < V CHG_VLIM YES ADP5061 ...
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... ADP5061 WATCHDOG EXPIRED YES t START SAFE I = 100 mA BUS TFAULT OR BAD BATTERY RUN BATTERY DETECTION YES V = BAT_SNS V RCH NO TO CHARGING MODE RUN BATTERY DETECTION YES NO V BAT_SNS < V TRK TRICKLE FAST CHARGE CHARGE NO VINOK YES NO V BAT_SNS < V TRK YES t EXPIRED WD TEMP < T ...
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... C stop as shown in Figure 35 read sequence of a single register. sends the data from the register denoted by the MASTER STOP 0 SP ADP5061 RECEIVES DATA 0 ADP5061 RECEIVES ADP5061 RECEIVES DATA TO LAST REGISTER MASTER 1 = READ STOP ADP5061 SENDS DATA 0 0 ...
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... ADP5061 REGISTER MAP See the Factory Programmable Options section for programming option details. Note that a blank cell indicates a bit that is not used. Table 17 Register Map Register Addr. Name D7 D6 0x00 Manufac- turer and model ID 0x01 Silicon revision 0x02 ...
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... Rev Page ADP5061 ...
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... ADP5061 Table 21. Termination Settings, Register Address 0x03 Bit No. Bit Name Access [7:2] VTRM[5:0] R/W [1:0] CHG_VLIM[1:0] R/W Default Description 100011 = 4.20 V Termination voltage programming bus. The values of the float voltage can be programmed to the following values: 001111 = 3.80 V. 010000 = 3.82 V. 010001 = 3.84 V. 010010 = 3.86 V. 010011 = 3.88 V. 010100 = 3.90 V. 010101 = 3.92 V. 010110 = 3.94 V. 010111 = 3.96 V. 011000 = 3.98 V. 011001 = 4.00 V. ...
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... Recharge voltage programming bus. The values of the recharge threshold can be programmed to the following values (note that the recharge cycle can be disabled mV 140 mV 200 mV 260 mV. Rev Page ADP5061 the DIS_RCH bit): ...
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... When RESET_WD is set to logic high by I timer is reset. Default Description normal operation the ADP5061 is disabled when V < V VIN VIN_OK 4.0 to 6.7 V, the battery monitor is enabled regardless of the EN_BMON state the battery monitor is enabled even when the voltage at the ...
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... VINx pin voltage thresholds interrupt is disabled VINx pin voltage thresholds interrupt is enabled. Rev Page ADP5061 threshold. CHG_VLIM < ISO_S ISO_B < V and V > ...
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... ADP5061 Table 28. Interrupt Active Register, Register Address 0x0A Bit No. Mnemonic 7 Not used 6 THERM_LIM_INT 5 WD_INT 4 TSD_INT 3 THR_INT 2 BAT_INT 1 CHG_INT 0 VIN_INT Table 29. Charger Status Register 1, Register Address 0x0B Bit No. Mnemonic 7 VIN_OV 6 VIN_OK 5 VIN_ILIM 4 THERM_LIM 3 CHDONE [2:0] CHAGER_STATUS[2:0] Access Default Description indicates an interrupt caused by isothermal charging. ...
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... Battery short timeout timer. 000 = 1 sec. 001 = 2 sec. 010 = 4 sec. 011 = 10 sec. 100 = 30 sec. 101 = 60 sec. 110 = 120 sec. 111 = 180 sec. 100 = 2.4 V Battery short voltage threshold level. 000 = 2.0 V. 001 = 2.1 V. 010 = 2.2 V. 011 = 2.3 V. 100 = 2.4 V. 101 = 2.5 V. 110 = 2.6 V. 111 = 2.7 V. Rev Page ADP5061 . . . TRK < WEAK . WEAK ...
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... ADP5061 Table 33. IEND Register, Register Address 0x11 Bit No. Mnemonic Access [7:5] IEND[2:0] R/W 4 C/20 EOC R/W 3 C/10 EOC R/W 2 C/5 EOC R/W 1:0 SYS_EN_SET[1:0] R/W 1 This option is active when VINx = 0 V and the battery monitor is activated from Register 0x07, Bit D5 (EN_BMON). Default Description 010 = 52.5 mA Termination current programming bus. The values of the termination current can be programmed to the following values: 000 = 12 ...
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... Rev Page 34.3 μF × (1 − 0.15) × (1 − 0.2) ≈ 20.7 μF ADP5061 ISO_Sx output should be ISO_Sx VIN1 C C ISO_S IN1 ≥10µF IC1 SUM OF EFFECTIVE CAPACITANCES ON ISO_Sx NODE ≥ 20µF C ISO_B ≥10µF VIN2 C IN2 IC2 Figure 39. Splitting ISO_Sx Capacitance ADP5061 is equipped with a ADP5061 ...
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... USB port. The peripheral device VBUS bypass capacitance must be at least 1 µF but not larger than 10 µF. The VINx input of the ADP5061 is tolerant of voltages as high however application requires exposing the VINx input to voltages the voltage range of the capacitor must also be above 20 V ...
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... CHARGER CONTROL BLOCK A4 SCL SDA A3 DIG_IO1 E4 DIG_IO2 C4 ISO_B1:3 B4 DIG_IO3 BAT_SNS THR SYS_EN A2 ILED A1 ADP5061 WLCSP20 AGND B1 Figure 40. Reference Circuit Diagram ISO_S ISO_B C 47µF C ISO_S PGND C 10µF VIN VIN 8mm Figure 41. Reference PCB Floor Plan Rev Page 47µ ...
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... ADI Reliability Handbook located at the following URL: ISO_SFC www.analog.com/reliability_handbook. , the ISO_SFC Rev Page × I DSON ISO CHG is the on resistance of the battery isolation FET ADP5061 automatically limits ADP5061 device is to measure the power , is known, the A , can be used to estimate the JA is calculated from × θ ...
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... Data Sheet FACTORY PROGRAMMABLE OPTIONS CHARGER OPTIONS Table 38 to Table 50 list the factory programmable options of the ADP5061. In each of these tables, the selection column represents the default setting of Model ADP5061ACBZ-2-R7. Table 38. Default Termination Voltage Option Selection 000 = 4.20 V 000 = 4.20 V 010 = 3.70 V 011 = 3.80 V 100 = 3.90 V 101 = 4.00 V 110 = 4 ...
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... ADP5061 I C REGISTER DEFAULTS 2 Table 47 Register Default Settings 2 Bit Name I C Register Address, Bit Location 2 CHG_VLIM Address 0x03, Bits[D1:D0] DIS_RCH Address 0x05, Bit D7 EN_WD Address 0x06, Bit D2 DIS_IC1 Address 0x07, Bit D6 EN_CHG Address 0x07, Bit D0 EN_JEITA Address 0x08, Bit D7 JEITA_SELECT ...
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... Fast charge current, low = ICHG, Interrupt output high = ICHG/2 Low = LDO active, high = LDO Interrupt output disabled Low = charging disabled, Interrupt output high = charging enabled Low = charging disabled, Interrupt output high = charging enabled Rev Page ADP5061 Selection 0 = high active Selection 0000 ...
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... SEATING PLANE ORDERING GUIDE Model 1, 2 Temperature Range ADP5061ACBZ-2-R7 –40°C to +125°C ADP5061CB-EVALZ RoHS Compliant Part. For additional factory programmable options, contact a local Analog Devices, Inc., sales or distribution representative 2 2.035 1.995 1.955 2.635 2.595 2.00 REF 2.555 ...
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... Data Sheet NOTES Rev Page ADP5061 ...
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... ADP5061 NOTES ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10544-0-6/12(0) Rev Page Data Sheet www.analog.com/ADP5061 ...