R2J20602NP-G3 RENESAS [Renesas Technology Corp], R2J20602NP-G3 Datasheet
R2J20602NP-G3
Related parts for R2J20602NP-G3
R2J20602NP-G3 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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... Integrated Driver – MOS FET (DrMOS) Description The R2J20602NP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap Schottky barrier diode (SBD), eliminating the need for an external SBD for this purpose ...
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... R2J20602NP Block Diagram DISBL# 2 µA CGND VCIN Input logic (TTL level) PWM (3 state in) CGND Notes: 1. Truth table for the DISBL# pin. DISBL# Input “L” Shutdown (GL “L”) “Open” Shutdown (GL “L”) “H” Enable (GL “Active”) 2. Output signal from the UVL block " ...
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... R2J20602NP Pin Arrangement VIN 15 VIN 16 VIN 17 VIN 18 VIN 19 VIN 20 VSWH 21 PGND 22 PGND 23 PGND 24 PGND 25 PGND 26 PGND 27 PGND 28 Note: All die-pads (three pads in total) should be soldered to PCB. Pin Description Pin Name Pin No. CGND 1, 6, 51, Tab Control signal ground connect VLDRV ...
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... R2J20602NP Absolute Maximum Ratings Item Power dissipation Average output current Input voltage Supply voltage Low side driver voltage Switch node voltage BOOT voltage DISBL# voltage PWM voltage Reg5V current Operating junction temperature Storage temperature Notes: 1. Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C. ...
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... R2J20602NP Electrical Characteristics (Ta = 25C, VCIN = 12 V, VLDRV = 5 V, VSWH = 0 V, unless otherwise specified) Item Supply VCIN start threshold VCIN shutdown threshold UVLO hysteresis VCIN bias current VLDRV bias current PWM PWM rising threshold Input PWM falling threshold PWM input resistance ...
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... GH GL VCIN VLDRV BOOT DISBL# VIN Reg5V VSWH R2J20602NP PWM PGND CGND GH GL VCIN BOOT VLDRV DISBL# VIN Reg5V VSWH R2J20602NP PWM PGND CGND GH GL VCIN VLDRV BOOT DISBL# VIN Reg5V VSWH R2J20602NP PWM PGND CGND GH GL +1.3 V Signal Power GND GND ...
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... Efficiency = OUT IN P (DrMOS – P LOSS IN ° REJ03G1480-0500 Rev.5.00 Mar 12, 2010 Page VCIN VLDRV BOOT DISBL# VIN Reg5V VSWH R2J20602NP PWM PGND CGND GH GL × V × LDRV CIN CIN OUT Electric I O load Averaging Average Output Voltage ...
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... R2J20602NP Typical Data Power Loss vs. Output Current 12 VIN = VCIN = 12 V VLDRV = VOUT = 1 MHz PWM L = 0.45 µ Output Current (A) Power Loss vs. Output Voltage 1.5 VIN = 12 V VCIN = 12 V 1.4 VLDRV = MHz PWM L = 0.45 µ ...
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... R2J20602NP Typical Data (cont.) Power Loss vs. Output Inductance 1.20 1.15 1.10 1.05 1.00 0.95 VIN = 12 V VCIN = 12 V 0.90 VLDRV = 5 V VOUT = 1 MHz 0.85 PWM Iout = 25 A 0.80 0.1 0.2 0.3 0.4 0.5 0.6 Output Inductance (µH) Average ILDRV vs. Switching Frequency 250 VIN = 12 V VCIN = 12 V VOUT = 1.3 V 200 L = 0.45 µH Iout = 0 A 150 100 50 0 250 ...
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... R2J20602NP Description of Operation The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low-side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage ...
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... The GH and GL pins are the gate-monitor pins for each MOS FET. MOS FETs The MOS FETs incorporated in R2J20602NP are highly suitable for synchronous-rectification buck conversion. For the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin ...
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... R2J20602NP PCB Layout Example Figure 2 shows an example of a PCB layout for the R2J20602NP in application. The several ceramic capacitors (e.g. 10 F) close to VIN and PGND can be expected to decrease switching noise and improve efficiency. In that case, all sections of the GND pattern must be connected with other PCB layers via low impedances. Moreover, the wide VSWH pattern can be expected to have the effect of dissipating heat from the low-side MOS FET ...
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... R2J20602NP Footprint Example 4.30 3.60 3.10 0.45 0.90 3. REJ03G1480-0500 Rev.5.00 Mar 12, 2010 Page 0.5 Figure 3 Footprint Example (Unit: mm) ...
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... R2J20602NP Package Dimensions JEITA Package Code RENESAS Code P-HVQFN56-8x8-0.50 PVQN0056KA Index mark y Ordering Information Part Name R2J20602NP#G3 REJ03G1480-0500 Rev.5.00 Mar 12, 2010 Page Previous Code MASS[Typ.] — 0. Quantity 2500 pcs 42 43 3.0 0.0 0.3 1.0 Dimension in Millimeters ...
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Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained ...