IR5001 IRF [International Rectifier], IR5001 Datasheet

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IR5001

Manufacturer Part Number
IR5001
Description
UNIVERSAL ACTIVE ORING CONTROLLER
Manufacturer
IRF [International Rectifier]
Datasheet

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DESCRIPTION
N-channel power MOSFET driver for Active ORing and
reverse polarity protection applications. The output voltage
of the IR5001 is determined based on the polarity of the
voltage difference on its input terminals. In particular, if the
current flow through an N-channel ORing FET is from
source to drain, the output of the IR5001 will be pulled
high to Vcc, thus turning the Active ORing FET on. If the
current reverses direction and flows from drain to source
(due to a short-circuit failure of the source, for example),
the IC will quickly switch the Active ORing FET off. Typical
turn-off delay for the IR5001 is only 130nS, which helps to
minimize voltage sags on the redundant dc voltage.
input contain integrated high voltage resistors and internal
clamps. This makes the IR5001 suitable for applications at
voltages up to 100V, and with a minimum number of
external components.
APPLICATIONS
TYPICAL APPLICATION
+48V input
-48V input B
FET Check Pulse
-48V input A
-48V/-24V Input Active ORing for carrier class communication equipment
Reverse input polarity protection for DC-DC power supplies
24V/48V output active ORing for redundant AC-DC rectifiers
Low output voltage (12V, 5V, 3.3V...) active ORing for redundant DC-DC and AC-DC power supplies
Active ORing of multiple voltage regulators for redundant processor power
FET A Status
The IR5001 is a universal high-speed controller and
Both inputs to the IC (INN and INP) as well as Vline
Fet B Status
Figure 1 - Typical application of the IR5001 in - 48V input,
A
B
carrier class telecommunications equipment.
FETch
FETch
FETst
Vline
Vcc
FETst
Vline
Vcc
IR5001
IR5001
Vout
Vout
Gnd
Gnd
INN
INN
INP
INP
UNIVERSAL ACTIVE ORING CONTROLLER
www.irf.com
DC
DC
FEATURES
Controller / driver IC in an SO-8 package for
implementation of Active ORing / reverse polarity
protection using N-channel Power MOSFETs
Suitable for both input ORing (for carrier class
telecom equipment) as well as output ORing for
redundant DC-DC and AC-DC power supplies
130ns Typical Turn-Off delay time
3A Peak Turn-Off gate drive current
Asymmetrical offset voltage of the internal high-speed
comparator prevents potential oscillations at light load
Ability to withstand continuous gate short conditions
Integrated voltage clamps on both comparator inputs
allow continuous application of up to 100V
Option to be powered either directly from 36-75V
universal telecom bus (100V max), or from an
external bias supply and bias resistor
Input/Output pins to determine the state of the Active
ORing circuit and power system redundancy
PACKAGE / ORDERING
Ordering P/N
IR5001S
INFORMATION
FETch
FETst
Vline
Vcc
JA
1
2
3
4
Top View
=128 C/W
Data Sheet No.PD60229
8 - Pin SOIC
Package
8
7
6
5
Vout
INN
Gnd
INP
IR5001
1

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IR5001 Summary of contents

Page 1

... Gnd FETch INN FETst INP Fet B Status -48V input B Figure 1 - Typical application of the IR5001 in - 48V input, carrier class telecommunications equipment. UNIVERSAL ACTIVE ORING CONTROLLER FEATURES Controller / driver SO-8 package for implementation of Active ORing / reverse polarity protection using N-channel Power MOSFETs Suitable for both input ORing (for carrier class ...

Page 2

... IR5001 ABSOLUTE MAXIMUM RATINGS Vline Voltage Vcc Voltage Icc Current INN, INP Voltage FETch, FETst FETst Sink Current Junction Temperature Storage Temperature Range CAUTION: 1. Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied ...

Page 3

... Negative input pin of internal comparator. This pin should connect to the 6 INN drain of N-channel Active ORing MOSFET. 7 Gnd Ground pin of the IR5001. Output pin for the IR5001. This pin is used to directly drive the gate of the 8 Vout Active Oring N-Channel MOSFET. TEST CONDITION Vline=25V, IOH=50uA, V(INN)=-0.3V IOL=100mA, V(INN)=+0 ...

Page 4

... IR5001 BLOCK DIAGRAM 50K V 1 LINE Vcc 2 12V Shunt 5V Regulator 5V, V REF 1.25V Generator 70K INP 5 clamp 70K INN 6 clamp FETch 3 Figure 2 - Simplified block diagram of the IR5001. 4 UVLO 9V 5V 12V Level 3.5mV 28mV Shifter 5V 0.3V 1.25V 2uA www.irf.com V 8 OUT Gnd 7 FETst 4 ...

Page 5

... INP INN t d(on) 90% 50% 10 OUT -Vos Gnd INP INN V HYST Figure 4 - Input Comparator Hysteresis Definition 200mV INP INN t r Figure 5 - Dynamic Parameters. www.irf.com IR5001 V OUT V INN (V =Gnd) INP 10ns -50mV -90mV t d(off ...

Page 6

... IR5001 TYPICAL OPERATING CHARACTERISTICS 180 170 160 150 140 130 120 -40 - Temperature (°C) Figure 6 - Turn Off Delay vs. Junction Temperature 5.7 5.6 5.5 5.4 5.3 5.2 5.1 -40 - Temperature (°C) Figure 8 - Vos vs. Junction Temperature -40 - Temperature (°C) Figure 10 - INP, INN Input Hysteresis vs. Junction Temp. ...

Page 7

... Top: 125°C 1.5 Bottom: 1.25 1 0.75 0.5 0. 100 20 Figure 13 - I(Vline) vs. Vline and Junction Temperature 121.0 120.5 120.0 119.5 119.0 118.5 118.0 117.5 117.0 80 100 20 Figure 15 - Turn Off Delay vs. Vline at Room Temperature www.irf.com IR5001 85°C 25°C -40° 100 Vline ( 100 Vline (V) 7 ...

Page 8

... INN and INP pins to the source and drain terminals of the N-FET should be as short as possible. The (INP – INN) voltage difference determines the state of the Vout pin of the IR5001. When the body diode of the Active ORing N-FET is forward- biased and the current first starts flowing, the voltage difference INP – ...

Page 9

... In the IR5001, the FETch pin is an input pin that can be used to turn off the output of the IR5001: logic high signal on FETch will pull the Vout pin low, and turn-off the channel of the Active ORing N-FET. This will force the current to flow through the body diode, resulting in VINP – ...

Page 10

... However, any of the biasing schemes shown in Fig. 16 can be used. For input ORing in carrier-class communications boards, one IR5001 is used per feed. This is shown in Fig.1. An evaluation kit is available for typical system boards, with input voltages of negative 36V to negative 75V, and for power levels from 30W to about 300W ...

Page 11

... FET. PCB trace between the Vout pin and the gate of the N-FET should also be minimized. A minimum of 0.1uF decoupling capacitor must be connected from Vcc to Gnd of the IR5001and should be placed as close to the IR5001 as possible. Ground should be connected to the source of N-FET separately from the INP pin. ...

Page 12

... IR5001 8-Pin Surface Mount, Narrow Body PIN NO NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS. 12 (S) SOIC Package DETAIL-A 0.38 +/- 0.015 x 45° 8-PIN SYMBOL MIN MAX A 4.80 4.98 B 1.27 BSC C 0.53 REF D 0.36 0.46 E 3.81 3.99 F 1.52 1.72 G 0.10 0.25 7° BSC H I 0.19 0.25 J 5.80 6.20 K 0° 8° L 0.41 1.27 T 1.37 1.57 www.irf.com ...

Page 13

... IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 PIN PARTS COUNT PER TUBE Feed Direction Figure A Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 4/8/2005 www.irf.com IR5001 PARTS T & R PER REEL Orientation 2500 Fig A TAC Fax: (310) 252-7903 13 ...

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