STTS424E02BDA3E STMICROELECTRONICS [STMicroelectronics], STTS424E02BDA3E Datasheet
STTS424E02BDA3E
Related parts for STTS424E02BDA3E
STTS424E02BDA3E Summary of contents
Page 1
Features ■ STTS424E02 includes a JEDEC JC 42.4 compatible temperature sensor, integrated with industry standard 2 Kbit Serial Presence Detect (SPD) EEPROM Temperature sensor ■ Temperature sensor resolution: 0.25°C (typ)/LSB ■ Temperature sensor accuracy: – ± 1°C from +75°C to ...
Page 2
Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
STTS424E02 5 SPD EEPROM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
STTS424E02 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
Description 1 Description The STTS424E02 is targeted for DIMM Modules in Mobile Personal Computing Platforms (Laptops), Server Memory Modules and other industrial applications. The Thermal Sensor (TS) in the STTS424E02 is compliant with the JEDEC specification, which defines Memory Module ...
Page 7
STTS424E02 2 Serial communications The STTS424E02 has a simple 2-wire SMBus™/I which allows the user to access both the 2 Kbit serial EEPROM and the data in the temperature register at any time. It communicates via the serial interface with ...
Page 8
Serial communications Figure 1. Logic diagram 1. SDA and EVENT are open drain. Table 1. Signal names Pin Symbol SDA 6 SCL 7 EVENT SDA and ...
Page 9
STTS424E02 Figure 3. Block diagram 2Kb SPD EEPROM Software Write Protect Temperature Sensor ADC Capability Register Configuration Register Temperature Register Address Pointer Register Serial communications ...
Page 10
Serial communications 2.2 Pin descriptions 2.2.1 A0, A1, A2 A2, A1, and A0 are selectable address pins for the 3 LSBs of the I They can be set to V internally connected to the E2, E1, E0 (chip selects) of ...
Page 11
STTS424E02 3 Temperature sensor operation The temperature sensor continuously monitors the ambient temperature and updates the temperature data register at least eight times per second. Temperature data is latched internally by the device and may be read by software from ...
Page 12
Temperature sensor operation 2 Figure 4. SMBus/I C write to pointer register SCL SDA Start by Master 2 Figure 5. SMBus/I C write to pointer register, followed by a read data word 1 SCL SDA 0 0 Start by Master ...
Page 13
STTS424E02 Figure 6. SMBus/I SCL SDA SCL (continued) SDA (continued) 2 3.2 SMBus/I C slave sub-address decoding The physical address for the TS is different than that used by the EEPROM. The TS physical address is binary ...
Page 14
Temperature sensor operation 2 3.3 SMBus timing consideration In order for this device to be both SMBus- and I each specification. The requirements which enable this device to co-exist with devices on either an SMBus ...
Page 15
STTS424E02 Table 2. AC SMBus and I Symbol t Bus free time between stop (P) and start (S) conditions BUF Hold time after (repeated) start condition. After this t HD:STA period, the first clock cycle is generated. (1) t Repeated ...
Page 16
Temperature sensor registers 4 Temperature sensor registers The temperature sensor component is comprised of various user-programmable registers. These registers are required to write their corresponding addresses to the Pointer register. They can be accessed by writing to their respective addresses ...
Page 17
STTS424E02 Table 5. Pointer register select bits (type, width, and default values Name CAPA Thermal sensor capabilities CONF Configuration UPPER Alarm temperature upper boundary LOWER ...
Page 18
Temperature sensor registers Table 6. Capability register format Bit15 Bit14 RFU RFU Bit7 Bit6 RFU RFU Table 7. Capability register bit definitions Bit Basic capability 0 – Alarm and critical trips turned OFF. – Alarm and ...
Page 19
STTS424E02 4.2 Configuration register (read/write) The 16-bit Configuration register stores various configuration modes that are used to set up the sensor registers and configure according to application and JEDEC requirements (see Table 8 on page 19 4.2.1 Event thresholds All ...
Page 20
Temperature sensor registers Table 9. Configuration register bit definitions Bit Event mode 0 – Comparator output mode (this is the default). – Interrupt mode; when either of the lock bits is set, this bit cannot be ...
Page 21
STTS424E02 Figure 8. Hysteresis Below Window bit Above Window bit Value stored in the alarm temperature upper boundary trip register Value stored in the alarm temperature lower boundary trip register HYS ...
Page 22
Temperature sensor registers 4.2.5 Event output pin functionality The Event outputs can be programmed to be configured as either a comparator output interrupt. This is done by enabling the Output Control bit (Bit 3) and setting the ...
Page 23
STTS424E02 Figure 9. Event output boundary timings T CRIT T UPPER LOWER Comparator Interrupt S/W Int. Clear Critical Table 11. Legend for Note Event output boundary conditions When ...
Page 24
Temperature sensor registers 4.3 Temperature register (read-only) This 16-bit, Read-only register stores the temperature measured by the internal band gap TS as shown inTable requirement. When reading this register, the MSBs (Bit 15 to Bit 8) are read first, and ...
Page 25
STTS424E02 Table 13. Temperature register bit definitions Bit Below (temperature) alarm window 13 – Temperature is equal to or above the alarm window lower boundary temperature. – Temperature is below the alarm window. Above (temperature) alarm ...
Page 26
Temperature sensor registers Table 16. Alarm temperature lower boundary register format Bit Bit Bit Table 17. Critical temperature register format Bit Bit Bit 26/51 Sign MSB Bit Bit ...
Page 27
STTS424E02 4.5 Manufacturer ID register (read-only) The Manufacturer’s ID (Programmed Value 104Ah) in this register is the STMicroelectronics Identification provided by the Peripheral Component Interconnect Special Interest Group (PCiSIG). Table 18. Manufacturer ID register format Bit15 Bit14 0 0 Bit7 ...
Page 28
SPD EEPROM operation 5 SPD EEPROM operation 5 SPD EEPROM operation The 2 Kbit serial EEPROM is able to lock permanently the data in its first half (from location 00h to 7Fh). This facility has been designed specifically ...
Page 29
STTS424E02 Prior to selecting the memory and issuing instructions, a valid and stable V be applied. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion ...
Page 30
SPD EEPROM operation Table 21. Operating modes Mode Current address read Random address read Sequential read Byte write Page write Figure 10. Result of setting the write protection Memory Area 5.4 ...
Page 31
STTS424E02 5.4.1 SWP and CWP If the software write-protection has been set with the SWP instruction, it can be cleared again with a CWP instruction. The two instructions (SWP and CWP) have the same format as a Byte Write instruction, ...
Page 32
SPD EEPROM operation 5.5.1 Byte write After the Device Select Code and the address byte, the bus master sends one data byte. If the addressed location is hardware write-protected, the device replies to the data byte with NoAck, and the ...
Page 33
STTS424E02 Figure 13. Write cycle polling flowchart using ACK First byte of instruction with already decoded by the device ReSTART STOP 5.5.3 Minimizing system delays by polling on ACK During the internal Write cycle, the device disconnects ...
Page 34
SPD EEPROM operation 5.6 Read operations - SPD Read operations are performed independently of whether hardware or software protection has been set. The device has an internal address counter which is incremented each time a byte is read. 5.6.1 Random ...
Page 35
STTS424E02 Figure 14. Read mode sequences - SPD CURRENT ADDRESS READ RANDOM ADDRESS READ SEQUENTIAL CURRENT READ SEQUENTIAL RANDOM READ 1. The seven most significant bits of the device select code of a random read (in the 1 be identical. ...
Page 36
Initial delivery state - SPD 6 Initial delivery state - SPD The device is delivered with all bits in the memory array set to ‘1’ (each byte contains FFh). 7 Use in a memory module In the Dual In line ...
Page 37
STTS424E02 7.1.2 DIMM inserted in the application motherboard As the final application cannot drive the A0 pin to V the write-protection with the PSWP instruction. Table 23 and Table 24 status. Table 23. Acknowledge when writing data or defining the ...
Page 38
Use in a memory module Table 24. Acknowledge when reading the write protection (instructions with R/W bit=1) Status Permanently PSWP, SWP or CWP protected Protected with SWP Not protected PSWP, SWP or CWP 38/51 Instruction Ack Address NoAck Not significant ...
Page 39
STTS424E02 8 Maximum ratings Stressing the device above the ratings listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions ...
Page 40
DC and AC parameters 9 DC and AC parameters This section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. The parameters in the dc and ac characteristics tables that follow, are derived from tests ...
Page 41
STTS424E02 Table 27. DC/AC characteristics - temperature sensor component with EEPROM (continued) Sym Description Accuracy for corresponding range B-grade 2.7 V ≤ V ≤ 3 Resolution t Conversion time CONV T Hysteresis HYS V Low level voltage OL1 ...
Page 42
Package mechanical data 10 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a halogen-free and lead-free second level interconnect. The category of second Level Interconnect is marked on the ...
Page 43
STTS424E02 Table 28. DFN8 – 8-lead dual flat, no-lead ( mm) mechanical data (DA) Sym ddd mm Min Typ Max 0.80 0.85 0.90 0.00 0.00 0.05 0.20 ...
Page 44
Package mechanical data Figure 16. TDFN8 – 8-lead thin dual flat, no-lead ( mm) package outline (DN) a. JEDEC MO-229, variation WCED-3 proposal 44/51 STTS424E02 (a) DA_ME ...
Page 45
STTS424E02 Table 29. TDFN8 – 8-lead thin dual flat, no-lead ( mm) mechanical data (DN) Sym ddd 1. JEDEC MO-229, variation WCED-3 proposal mm Min Typ Max ...
Page 46
Part numbering 11 Part numbering Table 30. Ordering information scheme Example: Device type STTS424E02 Grade B: Maximum accuracy 75°C to 95°C = ± 1°C C: Maximum accuracy 75°C to 95°C = ± 2°C Package DN = TDFN8 (0.80 mm max ...
Page 47
STTS424E02 12 Package marking information Figure 17. DA package topside marking information (DFN-8L) 1. Option codes accuracy grade. For example, E42C is C-grade. 2. Traceability codes P = Plant code Y = Year WW = ...
Page 48
Landing pattern 13 Landing pattern The landing pattern recommendations per the JEDEC proposal for the TDFN package (DN) are shown in Figure The preferred implementation with wide corner pads enhances device centering during assembly, but a narrower option is defined ...
Page 49
STTS424E02 Table 31 lists variations of landing pattern implementations, ranked as “Preferred” and Minimum Acceptable” based on the JEDEC proposal. Table 31. Parameters for landing pattern - TDFN package (DN) Parameter D2 Heat paddle width E2 Heat paddle height E3 ...
Page 50
Revision history 14 Revision history Table 32. Document revision history Date 13-Apr-2007 09-May-2007 04-Jun-2007 02-Jul-2007 18-Mar-2008 12-Jun-2008 50/51 Revision 1 Initial release. 2 Updated Table 27, 3 Updated Table 27. 4 Added POR threshold values to ...
Page 51
STTS424E02 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at ...