SC1218MLTRT SEMTECH [Semtech Corporation], SC1218MLTRT Datasheet - Page 9

• Manufacturer Part Number: SC1218MLTRT
• Description: High Speed Synchronous MOSFET Driver
• Manufacturer: SEMTECH [Semtech Corporation]

THEOR
THEOR
THEOR
THEOR
THEORY OF OPERA
The SC1218 is a high speed, robust, dual output driver
designed to drive top and bottom MOSFETs in a synchro-
nous Buck converter. It features internal bootstrap diode,
adaptive delay for shoot-through protection, 12V gate drive
voltage, and disable shutdown. It also supports dynamic
VID operation and CROWBAR function. This driver com-
bined with PWM controller SC2649 forms a multi-phase
voltage regulator for advanced microprocessors.
Star
Star
Star
Star
Startup and UVL
To startup the driver, a supply voltage is applied to the VIN
pin of the SC1218. The top and bottom gates are held
low until VIN exceeds the UVLO threshold of the driver,
typically 4.0V. The UVLO threshold has hysteresis, typi-
cally -250mV, to improve the nosie immunity from the VIN
pin.
Gat
Gat
Gate T
Gat
Gat
Refer to the Timing Diagrams section, the rising edge of
the PWM input initiates the turn-off of bottom FET and the
turn-on of top FET. After a short propagation delay (t
from PWM rising edge, the bottom gate falls (t
adaptive circuit in the SC1218 detects the bottom gate
voltage. It holds the top gate off until the bottom gate
voltage drops below 1.4V for a preset delay time (t
This prevents the top FET from turning on until the bottom
FET is off. During the transition, the inductor current is
freewheeling through the body diode of either bottom FET
or top FET, depended on the direction of the inductor cur-
rent. The phase node could be low (ground) or high (V
The falling edge of the PWM input controls the turn-off of
top FET and the turn-on of bottom FET.
propagation delay (t
gate falls (t
the top FET to the body diode of the bottom FET, the phase
node falls. The adaptive circuit in the SC1218 detects the
phase node voltage. It holds the bottom FET off until the
phase node voltage drops below 1.0V. This prevents the
top and bottom FETs from conducting simultaneously
(shoot-through). If the phase node voltage remains high
during the transition for a preset maximum BG turn on
delay (t
This supports the CROWBAR function and the sinking cur-
rent capacity required from dynamic VID operation.
Narrow PWM Pulse Filtering
Narrow PWM Pulse Filtering
Narrow PWM Pulse Filtering
Narrow PWM Pulse Filtering
Narrow PWM Pulse Filtering
During a load transient, soft start, or soft shutdown of the
voltage regulator, the PWM controller may generate a very
POWER MANAGEMENT
Applications Information
2005 Semtech Corp.
e T
e T
e Transition and Shoo
e T
tup and UVL
tup and UVL
tup and UVL
tup and UVLO O O O O
ransition and Shoo
ransition and Shoo
ransition and Shoot-thr
ransition and Shoo
Y OF OPERA
Y OF OPERA
Y OF OPERA
Y OF OPERATION
DH_MAX_BG
F_TG
). As the inductor current commutates from
) , then the bottom gate will be turned on.
PDL_TG
TION
TION
TION
TION
) from PWM falling edge, the top
t-thr
t-thr
t-thr
t-through Pr
ough Pr
ough Pr
ough Pr
ough Pro o o o o t t t t t ection
ection
ection
ection
ection
After a short
F_BG
). The
PDH_TG
PDL_BG
IN
).
).
)
9
Dynamic VID Operation
Dynamic VID Operation
Switching F
Switching F
Bootstrap and Chip Decoupling Capacitors
Bootstrap and Chip Decoupling Capacitors
narrow pulse for the driver. The pulse is so narrow that it
reaches the rising edge threshold of the SC1218 at one
point then immediately falls below the falling edge thresh-
old. To prevent the SC1218 from reacting to such narrow
PWM pulses, which may cause driver output ringing or
shoot through, advanced PWM timing circuitry is added to
ease the gate transitions. A minimum off-time (typically
140ns) for the bottom gate and a minimum on-time (typi-
cally 40ns) for the top gate are enforced to make the op-
eration safe under such conditions.
Dynamic VID Operation
Dynamic VID Operation
Dynamic VID Operation
Some processors changes VID dynamically during opera-
tion (Dynamic VID operation). A dynamic VID can occur
under light load or heavy load conditions. At light load, it
can force the converter to sink current. After turn-off of
the top FET, the reversed inductor current flows through
the body diode of the top FET instead of the bottom FET.
As a result, the phase node voltage remains high and voids
the adaptive circuit. SC1218 features a maximum BG
turn on delay (t
turn the bottom FET on. The preset maximum BG turn on
delay time (t
bottom gate turn-on is set to be 175ns.
Switching F
Switching F
Switching Freq
The SC1218 is capable of providing more than 3.5A peak
drive current, and operating up to 2MHz PWM frequency
without causing thermal stress on the driver. The selec-
tion of switching frequency, together with inductor and
FETs is a trade-off between the cost, size, and thermal
management of a multi-phase voltage regulator. Typically,
these parameters could be in the range of:
Bootstrap and Chip Decoupling Capacitors
Bootstrap and Chip Decoupling Capacitors
Bootstrap and Chip Decoupling Capacitors
The top gate driver of the SC1218 is a DRN refered gate
drive whose supply voltage is derived from a bootstrap
circuit comprising a capacitor,C
The capacitor value can be calculated based on the total
gate charge of the top FET, Q
ripple on the capacitor, V
a) Switching Frequency: 100kHz to 500kHz per phase
b) Inductor Value: 0.2uH to 2uH
c) MOSFETs: 4mOhm to 20mOhm R
to 100nC total gate charge
req
req
req
requency
DH_MAX_BG
DH_MAX_BG
uency
uency
uency
uency, Induct
) from the PWM falling egde to the
, Induct
, Induct
, Inductor and MOSFET
, Induct
C
) to override the adaptive delay to
BST
BST
>
, in one PWM cycle:
∆
Q
TOP
V
TOP
or and MOSFET
or and MOSFET
or and MOSFET
or and MOSFETs s s s s
BST
, and an allowed voltage
BST
, and a built-in diode.
DS(ON)
www.semtech.com
SC1218
and 20nC