AT90LS2343 ATMEL [ATMEL Corporation], AT90LS2343 Datasheet - Page 16

• Manufacturer Part Number: AT90LS2343
• Description: 8-Bit Microcontroller with 2K Bytes of In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Memory Access and
Instruction Execution
Timing
16
AT90S/LS2323/2343
This section describes the general access timing concepts for instruction execution and
internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the external
clock signal applied to the CLOCK pin. No internal clock division is used.
Figure 21. shows the parallel instruction fetches and instruction executions enabled by
the Harvard architecture and the fast-access register file concept. This is the basic pipe-
lining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks and functions per power unit.
Figure 21. The Parallel Instruction Fetches and Instruction Executions
Figure 22. shows the internal timing concept for the register file. In a single clock cycle
an ALU operation using two register operands is executed and the result is stored back
to the destination register.
Figure 22. Single Cycle ALU Operation
The internal data SRAM access is performed in two System Clock cycles as described
in Figure 23..
2nd Instruction Execute
3rd Instruction Execute
Register Operands Fetch
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
System Clock Ø
Result Write Back
System Clock Ø
T1
T1
T2
T2
T3
T3
1004D–09/01
T4
T4