AT90LS2343 ATMEL [ATMEL Corporation], AT90LS2343 Datasheet - Page 25

• Manufacturer Part Number: AT90LS2343
• Description: 8-Bit Microcontroller with 2K Bytes of In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

General Interrupt Flag
Register – GIFR
Timer/Counter Interrupt Mask
Register – TIMSK
Timer/Counter Interrupt FLAG
Register – TIFR
1004D–09/01
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the AT90S2323/2343 and always reads as zero.
• Bit 6 – INTF0: External Interrupt Flag0
When an edge on the INT0 pin triggers an interrupt request, the corresponding interrupt
flag, INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt
enable bit, INT0 in GIMSK, is set (one), the MCU will jump to the interrupt vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag is cleared by
writing a logical “1” to it. This flag is always cleared when INT0 is configured as level
interrupt.
• Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S2323/2343 and always read as zero.
• Bits 7..2 – Res: Reserved Bits
These bits are reserved bits in the AT90S2323/2343 and always read zero.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector
$002) is executed if an overflow in Timer/Counter0 occurs, i.e., when the Overflow Flag
(Timer/Counter0) is set (one) in the Timer/Counter Interrupt Flag Register (TIFR).
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the AT90S2323/2343 and always reads as zero.
• Bits 7..2 – Res: Reserved Bits
These bits are reserved bits in the AT90S2323/2343 and always read zero.
• Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0
(Ti mer /Counter 0 O v erfl ow Inte rr upt Enabl e) and TOV 0 ar e s et ( one ), the
Timer/Counter0 Overflow Interrupt is executed.
Bit
$3A ($5A)
Read/Write
Initial Value
Bit
$39 ($59)
Read/Write
Initial Value
Bit
$38 ($58)
Read/Write
Initial Value
R
7
–
0
R
7
–
0
R
7
–
0
INTF0
R/W
6
0
R
6
–
0
R
6
–
0
R
5
–
0
R
5
–
0
5
–
R
0
R
4
–
0
R
4
–
0
R
4
–
0
AT90S/LS2323/2343
R
3
–
0
R
3
–
0
R
3
–
0
R
2
–
0
R
R
2
–
0
2
–
0
TOIE0
TOV0
R/W
R/W
R
1
–
0
1
0
1
0
R
R
0
–
0
0
–
0
R
0
–
0
TIMSK
GIFR
TIFR
25