T89C51RD2-3CBC-L ATMEL [ATMEL Corporation], T89C51RD2-3CBC-L Datasheet

no-image

T89C51RD2-3CBC-L

Manufacturer Part Number
T89C51RD2-3CBC-L
Description
0 to 40MHz Flash Programmable 8-bit Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
0 to 40MHz Flash Programmable 8-bit Microcontroller
1. Description
ATMEL Wireless and Microcontrollers T89C51RD2 is
high performance CMOS Flash version of the 80C51
CMOS single chip 8-bit microcontroller. It contains a
64 Kbytes Flash memory block for program and for data.
The 64 Kbytes Flash memory can be programmed either
in parallel mode or in serial mode with the ISP capability
or with software. The programming voltage is internally
generated from the standard V
The T89C51RD2 retains all features of the ATMEL
Wireless and Microcontrollers 80C52 with 256 bytes of
internal RAM, a 7-source 4-level interrupt controller and
three timer/counters.
In addition, the T89C51RD2 has a Programmable
Counter Array, an XRAM of 1024 bytes, an EEPROM
of 2048 bytes, a Hardware Watchdog Timer, a more
versatile serial channel that facilitates multiprocessor
communication (EUART) and a speed improvement
2. Features
Rev. F - 15 February, 2001
80C52 Compatible
ISP (In System Programming) using standard V
power supply.
Boot
programming routines and a default serial loader
High-Speed Architecture
64K bytes on-chip Flash program / data Memory
On-chip 1024 bytes expanded RAM (XRAM)
8051 pin and instruction compatible
Four 8-bit I/O ports (or 6 in 64/68 pins packages)
Three 16-bit timer/counters
256 bytes scratch pad RAM
7 Interrupt sources with 4 priority levels
40 MHz in standard mode
20 MHz in X2 mode (6 clocks/machine cycle)
Byte and page (128 bytes) erase and write
10k write cycles
Software selectable size (0, 256, 512, 768, 1024
bytes)
768 bytes selected at reset for T87C51RD2
compatibility
FLASH
contains
CC
low
pin.
level
FLASH
CC
mechanism (X2 mode). Pinout is either the standard 40/
44 pins of the C52 or an extended version with 6 ports
in a 64/68 pins package.
The fully static design of the T89C51RD2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The T89C51RD2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the peripherals and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
The added features of the T89C51RD2 makes it more
powerful for applications that need
modulation, high speed I/O and counting capabilities
such as alarms, motor control, corded phones, smart card
readers.
Dual Data Pointer
Variable length MOVX for slow RAM/peripherals
Improved X2 mode with independant selection for
CPU and each peripheral
2 k bytes EEPROM block for data storage
Programmable Counter Array with:
Asynchronous port reset
Full duplex Enhanced UART
Hardware Watchdog Timer (One-time enabled with
Reset-Out)
Power control modes:
Low EMI (inhibit ALE)
100K Write cycle
High Speed Output,
Compare / Capture,
Pulse Width Modulator,
Watchdog Timer Capabilities
Idle Mode.
Power-down mode.
T89C51RD2
pulse width
1

Related parts for T89C51RD2-3CBC-L

T89C51RD2-3CBC-L Summary of contents

Page 1

... In the power-down mode the RAM is saved and all other functions are inoperative. The added features of the T89C51RD2 makes it more powerful for applications that need modulation, high speed I/O and counting capabilities such as alarms, motor control, corded phones, smart card readers ...

Page 2

... X1 Mode, 12MHz X2 Mode Temperature ranges: Commercial (0 to +70 C) and industrial (-40 to +85 C). Packages: PDIL40, PLCC44, VQFP44, PLCC68, VQFP64 PDIL40 PLCC44 Flash (bytes) VQFP44 1.4 T89C51RD2 64k PLCC68 Flash (bytes) VQFP64 1.4 T89C51RD2 64k 3. Block Diagram (3) XTAL1 XTAL2 ALE/ PROG PSEN CPU EA (3) ...

Page 3

... SFR Mapping The Special Function Registers (SFRs) of the T89C51RD2 fall into the following categories: C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 I/O port registers: P0, P1, P2, P3, P4, P5 Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H ...

Page 4

... T89C51RD2 reserved 4 Rev February, 2001 ...

Page 5

... P0.4/AD4 32 P0.5/AD5 31 P0.6/AD6 30 P0.7/AD7 29 EA VQFP44 1.4 28 NIC* 27 ALE/PROG 26 PSEN 25 P2.7/A15 24 P2.6/A14 23 P2.5/A13 T89C51RD2 P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 PLCC NIC* 33 ALE/PROG 32 PSEN 31 P2.7/A15 30 P2.6/A14 29 P2.5/A13 ...

Page 6

... T89C51RD2 P5.5 P0.3/AD3 P0.2/AD2 P5.6 P0.1/AD1 P0.0/AD0 P5.7 VCC VSS1 P1.0/T2 P4.0 P1.1/T2EX P1.2/ECI P1.3/CEX0 P4.1 P1.4/CEX1 P4.2 P5.5 P0.3/AD3 P0.2/AD2 P5.6 P0.1/AD1 P0.0/AD0 P5.7 VCC VSS1 P1.0/T2 P4.0 P1.1/T2EX P1.2/EC1 P1.3/CEX0 P4.1 P1.4/CEX1 NIC: No InternalConnection PLCC ...

Page 7

... Port 3 also serves the special features of the 80C51 family, as listed below. I RXD (P3.0): Serial input port O TXD (P3.1): Serial output port I INT0 (P3.2): External interrupt 0 I INT1 (P3.3): External interrupt (P3.4): Timer 0 external input I T1 (P3.5): Timer 1 external input O WR (P3.6): External data memory write strobe T89C51RD2 7 ...

Page 8

... T89C51RD2 Pin Number Mnemonic DIL LCC VQFP 1 Reset ALE/PROG PSEN XTAL1 XTAL2 Name and Function Type O RD (P3.7): External data memory read strobe I/O Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device ...

Page 9

... P4.1 24 P4.2 26 P4.3 44 P4.4 46 P4.5 50 P4.6 53 P4.7 57 P5.0 60 P5.1 62 P5.2 63 P5.3 7 P5.4 8 P5.5 10 P5.6 13 P5.7 16 Rev February, 2001 SQUARE 9/ T89C51RD2 9 ...

Page 10

... Some enhanced features are also located in the UART and the timer 2. 6.1. X2 Feature and Clock Generation The T89C51RD2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages: Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. ...

Page 11

... T89C51RD2 XTAL1 XTAL1:2 X2 bit CPU clock STD Mode The X2 bit in the CKCON register (See Table 2.) allows to switch from 12 clock periods per instruction to 6 clock periods and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode). ...

Page 12

... Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2" bits. Reset Value = X000 0000b Not bit addressable Rev February, 2001 T89C51RD2 Description 12 ...

Page 13

... ASSEMBLY LANGUAGE Rev February, 2001 DPTR1 DPTR0 DPH(83H) DPL(82H) Figure 3. Use of Dual Pointer Table 3. AUXR1: Auxiliary Register Operating Mode DPTR0 Selected DPTR1 Selected b . T89C51RD2 External Data Memory GF3 0 - DPS ...

Page 14

... T89C51RD2 ; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ...

Page 15

... Expanded RAM (XRAM) The T89C51RD2 provide additional Bytes of random access memory (RAM) space for increased data parameter handling and high level language usage. T89C51RD2 devices have expanded RAM in external data space; Maximum size and location are described in Table 4. Port XRAM size ...

Page 16

... T89C51RD2 The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory which is physically located on-chip, logically occupies the first bytes of external data memory. The bits XRS0 and XRS1 are used to hide a part of the available XRAM as explained in Table . This can be useful if external peripherals are mapped at addresses already used by the internal XRAM ...

Page 17

... Timer 2 The timer 2 in the T89C51RD2 is compatible with the timer 2 in the 80C52 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in cascade controlled by T2CON register (See Table 5) and T2MOD register (See Table 6). Timer 2 operation is similar to Timer 0 and Timer 1 ...

Page 18

... T89C51RD2 XTAL1 F XTAL Figure 5. Auto-Reload Mode Up/Down Counter (DCEN = 1) 6.4.2. Programmable Clock-Output In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 6) . The input clock increments TL2 at frequency F At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do not generate interrupts ...

Page 19

... RCAP2H and RCAP2L registers. XTAL1 T2 T2EX Rev February, 2001 :2 TR2 T2CON reg TL2 (8-bit) RCAP2L (8-bit) Toggle Q D T2OE T2MOD reg EXF2 T2CON reg EXEN2 T2CON reg Figure 6. Clock-Out Mode C/ T89C51RD2 TH2 (8-bit) OVEFLOW RCAP2H (8-bit) TIMER 2 INTERRUPT 19 ...

Page 20

... T89C51RD2 T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. ...

Page 21

... Set to program P1.0/T2 as clock output. Down Counter Enable bit 0 DCEN Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter. Reset Value = XXXX XX00b Not bit addressable Rev February, 2001 Table 6. T2MOD Register Description T89C51RD2 T2OE DCEN 21 ...

Page 22

... X2 Mode) The Timer 0 overflow The input on the ECI pin (P1.2) Rev February, 2001 mode mode) PCA component External I/O Pin 16-bit Counter P1.2 / ECI 16-bit Module 0 P1.3 / CEX0 16-bit Module 1 P1.4 / CEX1 16-bit Module 2 P1.5 / CEX2 16-bit Module 3 P1.6 / CEX3 16-bit Module 4 P1.7 / CEX4 T89C51RD2 22 ...

Page 23

... T89C51RD2 Fosc /12 Fosc / 4 T0 OVF P1.2 CIDL Idle CF Table 7. CMOD: PCA Counter Mode Register CMOD Address 0D9H Reset value Symbol Function Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during CIDL idle Mode. CIDL = 1 programs gated off during idle. ...

Page 24

... The value read from a reserved bit is indeterminate. The watchdog timer function is implemented in module 4 (See Figure 10). The PCA interrupt system is shown in Figure 8 Rev February, 2001 CCF4 CCF3 T89C51RD2 CCF2 CCF1 CCF0 ...

Page 25

... T89C51RD2 PCA Timer/Counter Module 0 Module 1 Module 2 Module 3 Module 4 CMOD.0 ECF PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform: 16-bit Capture, positive-edge triggered, 16-bit Capture, negative-edge triggered, 16-bit Capture, both positive and negative-edge triggered, 16-bit Software Timer, 16-bit High Speed Output, 8-bit Pulse Width Modulator ...

Page 26

... X CEXn 16-bit capture by a transition on CEXn 16-bit Software Timer / Compare mode 16-bit High Speed Output 8-bit PWM Watchdog Timer (module 4 only) T89C51RD2 MATn TOGn PWMm ECCFn Module Function 26 ...

Page 27

... T89C51RD2 Table 11. CCAPnH: PCA Modules Capture/Compare Registers High CCAP0H=0FAH CCAP1H=0FBH CCAPnH Address CCAP2H=0FCH CCAP3H=0FDH CCAP4H=0FEH Reset value Table 12. CCAPnL: PCA Modules Capture/Compare Registers Low CCAP0L=0EAH CCAP1L=0EBH CCAPnL Address CCAP2L=0ECH CCAP3L=0EDH CCAP4L=0EEH Reset value CH Address 0F9H Reset value CL Address 0E9H Reset value 6 ...

Page 28

... CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 10). Rev February, 2001 CCON CCF4 CCF3 CCF2 CCF1 CCF0 0xD8 Capture CCAPMn CAPNn MATn TOGn PWMn ECCFn 0xDA to 0xDE Figure 9. PCA Capture Mode T89C51RD2 PCA IT PCA Counter/Timer CH CL CCAPnH CCAPnL 28 ...

Page 29

... T89C51RD2 Write to CCAPnL Reset Write to CCAPnH CCAPnH Enable Only for Module 4 Figure 10. PCA Compare Mode and PCA Watchdog Timer Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit. ...

Page 30

... CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn Rev February, 2001 CF CR CCF4 CCF3 CCAPnL Match 16 bit comparator CL ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn T89C51RD2 CCON CCF2 CCF1 CCF0 0xD8 PCA IT CEXn CCAPMn 0xDA to 0xDE 30 ...

Page 31

... T89C51RD2 SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. ...

Page 32

... Serial I/O Port The serial I/O port in the T89C51RD2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates ...

Page 33

... T89C51RD2 RXD RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 Figure 15. UART Timings in Modes 2 and 3 6.6.2. Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt ...

Page 34

... SADEN - Slave Address Mask Register (B9h Reset Value = 0000 0000b Not bit addressable SADDR - Slave Address Register (A9h Reset Value = 0000 0000b Not bit addressable Rev February, 2001 1111 111Xb Table 15. SCON Register T89C51RD2 ...

Page 35

... T89C51RD2 SCON - Serial Control Register (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit Serial port Mode bit 0 Refer to SM1 for serial port mode selection ...

Page 36

... Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. Rev February, 2001 Table 16. PCON Register POF GF1 Description T89C51RD2 GF0 PD IDL 36 ...

Page 37

... Interrupt System The T89C51RD2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt and the PCA global interrupt. These interrupts are shown in Figure 16. INT0 IE0 TF0 INT1 IE1 TF1 ...

Page 38

... T89C51RD2 IPH low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced ...

Page 39

... Timer 0 overflow interrupt Priority bit 1 PT0 Refer to PT0H for priority level. External interrupt 0 Priority bit 0 PX0 Refer to PX0H for priority level. Reset Value = X000 0000b Bit addressable Rev February, 2001 Table 19. IP Register PT1 Description T89C51RD2 PX1 PT0 PX0 39 ...

Page 40

... T89C51RD2 IPH - Interrupt Priority High Register (B7h PPCH PT2H Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA interrupt priority bit high. PPCHPPC PPCH Timer 2 overflow interrupt Priority High bit ...

Page 41

... NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is not entered. Rev February, 2001 Power-down phase Oscillator restart phase Figure 17. Power-Down Exit Waveform T89C51RD2 CC Active phase 41 ...

Page 42

... T89C51RD2 This table shows the state of ports during idle and power-down modes. Program Mode ALE Memory Idle Internal Idle External Power Down Internal Power Down External * Port 0 can force a 0 level. A "one" will leave port floating. 42 PSEN PORT0 1 1 Port Data* ...

Page 43

... X Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. Rev February, 2001 7 counter has been added to extend the Time-out capability, ranking from Table 21. WDTRST Register T89C51RD2 , where make OSC OSC OSC ...

Page 44

... To ensure that the WDT does not overflow within a few states of exiting of powerdown best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the T89C51RD2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode ...

Page 45

... Pull ALE low while the device is in reset (RST high) and PSEN is high. Hold ALE low as RST is deactivated. While the T89C51RD2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit. Table 23. shows the status of the port pins during ONCE mode. ...

Page 46

... See Table 6. ALE Output bit 0 AO Clear to restore ALE operation during internal fetches. Set to disable ALE operation during internal fetches. Reset Value = XX0X 1000b Not bit addressable Rev February, 2001 Table 24. AUXR Register XRS1 Description T89C51RD2 XRS0 EXTRAM AO 46 ...

Page 47

... Launch the programming by writing the control sequence (52h or 50h followed by A2h or A0h) to the EECON register (see Table 25). EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that EEPROM segment is not available for read. The end of programming is signaled by a hardware clear of the EEBUSY flag. Rev February, 2001 T89C51RD2 47 ...

Page 48

... T89C51RD2 Example : ..... Wait : MOV A,EECON ANL A,#01h JNZ Wait MOV EETIM,#3Ch MOV EECON,#02h MOVX @DPTR,A MOV EECON,#50h or 52h ; Write Sequence MOV EECON,#A0h or A2h .... 7.4. Read Data The following procedure is used to read the data store in the EEPROM memory: Map the program space (Set bit EEE of EECON register) ...

Page 49

... The write timer register value is required to adapt the write time to the oscillator frequency 7-0 EETIM Value = 5 * Fxtal (MHz) in normal mode Fxtal in X2 mode. Example : Fxtal = 33 MHZ, EETIM = 0A5h Reset Value= 0000 0000b Rev February, 2001 Table 26. EETIM Register EETIM Description T89C51RD2 ...

Page 50

... Third, the FLASH may be programmed using the parallel method by using a conventional EPROM programmer. The parallel programming method used by these devices is similar to that used by EPROM 87C51 but it is not identical and the commercially available programmers need to have support for the T89C51RD2. Rev February, 2001 pins of the microcontroller ...

Page 51

... Reset Value = xxxx 0000b The Flash programming application note and API source code are available on request. 8.4.2. Hardware register The only hardware register of the T89C51RD2 is called Hardware Security Byte (HSB). After full FLASH erasure, the content of this byte is FFh; each bit is active at low level. 51 ...

Page 52

... When this bit is reset the boot address is FC03h. By default, this bit is cleared and the ISP is enabled. 8.4.2.2. FLASH memory lock bits The three lock bits provide different levels of protection for the on-chip code and data, when programmed according to Table 29. Rev February, 2001 Table 27. Hardware Security Byte (HSB Description T89C51RD2 LB2 LB1 LB0 52 ...

Page 53

... T89C51RD2 Program Lock Bits Security LB0 LB1 LB2 level No program lock features enabled. MOVC instruction executed from external program memory returns non encrypted data. MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory sampled and latched on reset, and further ...

Page 54

... FFh FCh 18h or 1Bh FFh 58h D7h FCh Device name and revi- FFh Table 30 Table 30. Software Security Byte (SSB LB1 - Description T89C51RD2 ATMEL Wireless and Microcontrollers C51 X2, Electrically Erasable T89C51RD2 memories size T89C51RD2 , revision 0 and Table LB0 54 ...

Page 55

... WARNING: Security level 2 and 3 should only be programmed after FLASH and code verification. 8.5. FLASH memory status T89C51RD2 parts are delivered in standard with the ISP boot in the FLASH memory. After ISP or parallel programming, the possible contents of the FLASH memory are summarized on the figure below: Figure 19 ...

Page 56

... At the falling edge of reset (unless the hardware conditions on PSEN, EA and ALE are set as described below), the T89C51RD2 reads the BLJB bit in the HSB byte. If this bit is set, it jumps to 0000h and if not, it jumps to FC03h. At this address, the boot software reads two special FLASH registers: the Software Boot Vector (SBV) and the Boot Status Byte (BSB). If the BSB is set to zero, power-up execution starts at location 0000h, which is the normal start address of the user’ ...

Page 57

... T89C51RD2 Boot process summary The boot process is summarized on the following flowchart: Reset Falling Edge Yes ( Hardware Conditions ? No Yes BLJB = Hardware Jump to FC03h Software BSB= 0 BSB ? BSB 00h SBV= FCh Software Boot Vector ? SBV FCh Jump to XX00h CUSTOM BOOT LOADER 57 PSEN =0, EA =1, and ALE =1 or not connected) ...

Page 58

... The operation indicated by the record type is not performed until the entire record has been received. Should an error occur in the checksum, the T89C51RD2 will send an “X” out the serial port indicating a checksum error. If the checksum calculation is found to match the checksum in the record, then the command will be executed. In most cases, successful reception of the record will be indicated by transmitting a “ ...

Page 59

... T89C51RD2 Table 32. Intel-Hex Records Used by In-System Programming RECORD TYPE Data Record :nnaaaa00dd....ddcc Where number of bytes (hex) in record 00 aaaa = memory address of first byte in record dd....dd = data bytes cc = checksum Example: :05008000AF5F67F060B6 (program address 80h to 85h with data AF ... 60) End of File (EOF), no operation ...

Page 60

... Device Data or Blank Check” function code ssss = starting address eeee = ending address ff = subfunction 00 = display data 01 = blank check cc = checksum Example: :0500000440004FFF0069 (display 4000–4FFF) Rev February, 2001 T89C51RD2 60 ...

Page 61

... T89C51RD2 Table 32. Intel-Hex Records Used by In-System Programming Miscellaneous Read Functions General Format of Function 05 :02xxxx05ffsscc Where number of bytes (hex) in record xxxx = required field, but value is a “don’t care” 05= “Miscellaneous Read” function code ffss = subfunction and selection code 0000 = read copy of the signature byte – manufacturer id (58H) 05 0001 = read copy of the signature byte – ...

Page 62

... Return Parameter ACC = value of byte read Input Parameters osc freq (integer Not required, left for Philips compatibility 00h READ copy of the DPH = 00h MANUFACTURER ID DPL = 00h (manufacturer ID) Return Parameter ACC = value of byte read Rev February, 2001 Table 33. API calls T89C51RD2 62 ...

Page 63

... T89C51RD2 API call Input Parameters osc freq (integer Not required, left for Philips compatibility 00h READ copy of the device DPH = 00h DPL = 01h (device Return Parameter ACC = value of byte read Input Parameters osc freq (integer Not required, left for Philips compatibility) ...

Page 64

... XAF in order to make their values accessible by software (ISP or API). 8.9.2. Set-up modes In order to program and verify the FLASH or to read the signature bytes, the T89C51RD2 is placed in specific set-up modes (See Figure 22). Control and program signals must be held at the levels indicated in Table 37. and Table 38.(Please notice that each mode is defined over the two tables Rev ...

Page 65

... T89C51RD2 Mode Name Mode Program or Erase Lock. PELCK Disable the Erasure or Programming access Program or Erase UnLock. PEULCK Enable the Erasure or Programming access Write Code Data (byte) PGMC or write Page Always precedeed by PGML Memory Page Load PGML (up to 128 bytes) PGMV Read Code Data (byte) ...

Page 66

... A7-A0 A13- A7- (0-7F) A7- (0-7F) 30h 31h 60h 61h Addr (0-7F) T89C51RD2 P3.2 P3.3 P3.4 P3 Note1 0 A14 A15 x 0 A14 A15 x 1 A14 A15 Note1 Note1 ...

Page 67

... CONTROL SIGNALS MHz 8.9.4. Programming Algorithm To program the T89C51RD2 the following sequence must be exercised: Check the signature bytes Check the HSB (VSB mode) If the security bits are activated, the following commands must be done before programming: Unlock test modes (PEULCK mode, pulse 55h and AAh) ...

Page 68

... Control signals P2.7 Figure 23. Programming and Verification Signal’s Waveform 8.9.6. Extra memory mapping The memory mapping the T89C51RD2 software registers in the Extra FLASH memory is described in the table below. Table 34. Extra Row Memory Mapping (XAF) Copy of device ID #3 Rev February, 2001 Read/Verify Cycle ...

Page 69

... T89C51RD2 Table 34. Extra Row Memory Mapping (XAF) Copy of device ID #2 Copy of device ID #1 ATMEL Copy of Manufacturer Code: Boot reference Software Security Byte (level 1 by default) Copy of HSB (level 4 by default and BLJB = 0) Software Boot Vector Boot Status Byte All other addresses are reserved ...

Page 70

... Exposure to absolute maximum rating conditions may affect device reliability. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package. Rev February, 2001 (1) +0 T89C51RD2 70 ...

Page 71

... T89C51RD2 9.2. DC Parameters for Standard Voltage ( + - + Symbol Parameter V Input Low Voltage IL V Input High Voltage except XTAL1, RST IH V Input High Voltage, XTAL1, RST IH1 V Output Low Voltage, ports and 5 ...

Page 72

... Table 36. DC Parameters for Standard Voltage (2) Rev February, 2001 = 5 MHz 5 MHz. CC Min (5) Typ -0.5 0 0 (6) ( 120 T89C51RD2 Max Unit Test Conditions 0. 0.45 V ...

Page 73

... T89C51RD2 9.4. DC Parameters for Low Voltage + - + Symbol Parameter V Input Low Voltage IL V Input High Voltage except XTAL1, RST IH V Input High Voltage, XTAL1, RST IH1 V Output Low Voltage, ports and 5 ...

Page 74

... CLOCK XTAL1 SIGNAL V SS Figure 25. I Test Condition, Idle Mode RST EA (NC) XTAL2 XTAL1 V SS Test Condition, Power-Down Mode CC T89C51RD2 All other pins are disconnected. All other pins are disconnected. All other pins are disconnected. 74 ...

Page 75

... T89C51RD2 Figure 27. Clock Signal Waveform for I 9.5. AC Parameters 9.5.1. Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for ...

Page 76

... LLAX T LLIV T 15 LLPL T 55 PLPH T PLIV T 0 PXIX T PXIZ T AVIV T PLAZ Rev February, 2001 Table 38. Symbol Description Parameter -M -L Max Min T89C51RD2 Units Max ...

Page 77

... T89C51RD2 Table 40. AC Parameters for a Variable Clock Symbol Type T Min LHLL T Min AVLL T Min LLAX T Max LLIV T Min LLPL T Min PLPH T Max PLIV T Min PXIX T Max PXIZ T Max AVIV T Max PLAZ 9.5.3. External Program Memory Read Cycle T LHLL ALE PSEN T PORT 0 INSTR IN ...

Page 78

... ALE LLWL T Address AVWL T Data Valid to WR Transition QVWX T Data set- High QVWH T Data Hold After WR WHQX T RD Low to Address Float RLAZ High to ALE high WHLH Rev February, 2001 Table 41. Symbol Description Parameter T89C51RD2 78 ...

Page 79

... T89C51RD2 Table 42. AC Parameters for a Fix Clock Symbol Min T 130 RLRH T 130 WLWH T RLDV T 0 RHDX T RHDZ T LLDV T AVDV T 50 LLWL T 75 AVWL T 10 QVWX T 160 QVWH T 15 WHQX T RLAZ T 10 WHLH Max Min 130 130 100 0 30 160 165 ...

Page 80

... LLWL T QVWX T LLAX A0-A7 T AVWL ADDRESS A8-A15 OR SFR P2 T89C51RD2 X parameter Units for -L range ...

Page 81

... T89C51RD2 9.5.6. External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 9.5.7. Serial Port Timing - Shift Register Mode Symbol T XLXL T QVHX T XHQX T XHDX T XHDV Table 45. AC Parameters for a Fix Clock Symbol Min T 300 XLXL T 200 QVHX T 30 XHQX T 0 XHDX ...

Page 82

... XLXL T XHQX XHDX VALID VALID VALID VALID T89C51RD2 X parameter Units for -L range 133 133 SET TI VALID VALID ...

Page 83

... T89C51RD2 9.5.9. FLASH EEPROM Programming and Verification Characteristics 0V Table 47. Flash Programming Parameters Symbol Parameter 1/T Oscillator Frquency CLCL T Control to address float EHAZ T Address Setup to PROG Low AVGL T PROG Adress Hold after GHAX T Data Setup to PROG Low DVGL T Data ...

Page 84

... CLCL 0 0 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement CC max for a logic “0”. IL FLOAT - 0 LOAD LOAD + 0 LOAD /V level occurs T89C51RD2 Max Units CHCX T CLCH + 0 0 20mA ...

Page 85

... T89C51RD2 9.5.15. Clock Waveforms Valid in normal clock mode mode XTAL2 must be changed to XTAL2/2. STATE4 STATE5 INTERNAL CLOCK XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA PCL OUT SAMPLED FLOAT P2 (EXT) INDICATES ADDRESS TRANSITIONS READ CYCLE RD P0 DPL OR Rt OUT ...

Page 86

... S Temperature Range C: Commercial Industrial - Conditioning S: Stick T: Tray R: Tape & Reel U: Stick + Dry Pack V: Tray + Dry Pack F: Tape & Reel + Dry Pack B: Blue Tape W: Wafer T89C51RD2 -M: VCC: 4.5 to 5.5V 40MHz, X1 Mode 20MHz, X2 Mode VCC 5.5V 33 MHz, X1 mode 16 MHz, X2 mode -L : VCC: 2 ...

Related keywords