ATMEGA48V_11 ATMEL [ATMEL Corporation], ATMEGA48V_11 Datasheet - Page 138

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ATMEGA48V_11

Manufacturer Part Number
ATMEGA48V_11
Description
8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
ATmega48/88/168
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
< f
/2) given a 50/50% duty cycle. Since the edge detector uses
ExtClk
clk_I/O
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
/2.5.
clk_I/O
An external clock source can not be prescaled.
(1)
Figure 17-2. Prescaler for timer/counter0 and timer/counter1
.
clk
I/O
Clear
PSRSYNC
T0
Synchronization
T1
Synchronization
clk
clk
T1
T0
T1/T0)
Note:
1. The synchronization logic on the input pins (
is shown in
Figure 17-1 on page
137.
138
2545T–AVR–05/11

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