ATMEGA48V_11 ATMEL [ATMEL Corporation], ATMEGA48V_11 Datasheet - Page 171

• Manufacturer Part Number: ATMEGA48V_11
• Description: 8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

20. USART0
20.1
20.2
2545T–AVR–05/11
Features
Overview
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The USART can also be used in Master SPI mode,
Power Reduction USART bit, PRUSART0, in
be disabled by writing a logical zero to it.
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device.
A simplified block diagram of the USART Transmitter is shown in
accessible I/O Registers and I/O pins are shown in bold.
The dashed boxes in the block diagram separate the three main parts of the USART (listed from
the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.
The Clock Generation logic consists of synchronization logic for external clock input used by
synchronous slave operation, and the baud rate generator. The XCKn (Transfer Clock) pin is
only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a
serial Shift Register, Parity Generator and Control logic for handling different serial frame for-
mats. The write buffer allows a continuous transfer of data without any delay between frames.
The Receiver is the most complex part of the USART module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level
receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and
can detect Frame Error, Data OverRun and Parity Errors.
Full duplex operation (independent serial receive and transmit registers)
Asynchronous or synchronous operation
Master or slave clocked synchronous operation
High resolution baud rate generator
Supports serial frames with 5, 6, 7, 8, or 9 data bits, and 1 or 2 stop bits
Odd or even parity generation and parity check supported by hardware
Data overrun detection
Framing error detection
Noise filtering includes false start bit detection and digital low pass filter
Three separate interrupts on TX complete, TX data register empty and RX complete
Multi-processor communication mode
Double speed asynchronous communication mode
“Minimizing power consumption” on page 41
see “USART in SPI mode” on page
ATmega48/88/168
Table 20-1 on page
172. CPU
199. The
must
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