ATMEGA48V_11 ATMEL [ATMEL Corporation], ATMEGA48V_11 Datasheet - Page 173

• Manufacturer Part Number: ATMEGA48V_11
• Description: 8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

20.3.1
2545T–AVR–05/11
Internal clock generation – The baud rate generator
Figure 20-2. Clock generation logic, block diagram.
Signal description:
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to
The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(f
the UBRRnL Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= f
baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-
put is used directly by the Receiver’s clock and data recovery units. However, the recovery units
use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSELn, U2Xn and DDR_XCKn bits.
osc
), is loaded with the UBRRn value each time the counter has counted down to zero or when
tx
rx
x
x
f
osc
cki
cko
DDR_XCKn
clk
clk
XCKn
pin
xcko
xcki
OSC
operation.
Transmitter clock (internal signal).
Receiver base clock (internal signal).
Input from XCK pin (internal signal). Used for synchronous slave
Clock output to XCK pin (internal signal). Used for synchronous master
operation.
System clock frequency.
down-counter
Prescaling
register
UBRRn
Sync
UBRRn+1
foscn
detector
UCPOLn
Edge
/2
Figure
osc
/(UBRRn+1)). The Transmitter divides the
/4
20-2.
ATmega48/88/168
/2
DDR_XCKn
U2Xn
0
1
0
1
0
1
1
0
UMSELn
txclk
rxclk
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