ATMEGA48V_11 ATMEL [ATMEL Corporation], ATMEGA48V_11 Datasheet - Page 193
ATMEGA48V_11
Manufacturer Part Number
ATMEGA48V_11
Description
8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATMEGA48V_11.pdf
(377 pages)
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2545T–AVR–05/11
• Bits 5:4 – UPMn1:0: Parity mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Table 20-5.
• Bit 3 – USBSn: Stop bit select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Table 20-6.
• Bit 2:1 – UCSZn1:0: Character size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Table 20-7.
• Bit 0 – UCPOLn: Clock polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCKn).
UCSZn2
UPMn1
0
0
1
1
0
0
0
0
1
1
1
1
UPMn bits settings.
USBS bit settings.
UCSZn bits settings.
USBSn
0
1
UCSZn1
UPMn0
0
1
0
1
0
0
1
1
0
0
1
1
Parity mode
Disabled
Reserved
Enabled, even parity
Enabled, odd parity
Stop bit(s)
1-bit
2-bit
UCSZn0
0
1
0
1
0
1
0
1
ATmega48/88/168
Character size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
193
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