ATMEGA48V_11 ATMEL [ATMEL Corporation], ATMEGA48V_11 Datasheet - Page 239

• Manufacturer Part Number: ATMEGA48V_11
• Description: 8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

22.9.5
22.9.6
2545T–AVR–05/11
TWAR – TWI (slave) address register
TWAMR – TWI (slave) address mask register
of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the
ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.
• Bits 7..0 – TWD: TWI data register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received
on the 2-wire Serial Bus.
The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of
TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver,
and not needed in the Master modes. In multi master systems, TWAR must be set in masters
which can be addressed as Slaves by other Masters.
The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an
associated address comparator that looks for the slave address (or general call address if
enabled) in the received serial address. If a match is found, an interrupt request is generated.
• Bits 7..1 – TWA: TWI (slave) address register
These seven bits constitute the slave address of the TWI unit.
• Bit 0 – TWGCE: TWI general call recognition enable bit
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.
• Bits 7..1 – TWAM: TWI address mask
The TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR can
mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If the mask
bit is set to one then the address match logic ignores the compare between the incoming
address bit and the corresponding bit in TWAR.
match logic in detail.
Bit
(0xBA)
Read/write
Initial value
Bit
(0xBD)
Read/write
Initial value
TWA6
R/W
R/W
7
0
7
1
TWA5
R/W
R/W
6
0
6
1
TWA4
R/W
R/W
5
0
5
1
TWAM[6:0]
TWA3
R/W
R/W
4
0
4
1
Figure 22-22 on page 240
TWA2
R/W
R/W
3
0
3
1
TWA1
R/W
R/W
ATmega48/88/168
2
0
2
1
TWA0
R/W
R/W
1
0
1
1
shown the address
TWGCE
R/W
R
0
–
0
0
0
TWAMR
TWAR
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