ATXMEGA128B3-AU

Manufacturer Part NumberATXMEGA128B3-AU
Description8/16-bit Atmel XMEGA B3 Microcontroller
ManufacturerATMEL [ATMEL Corporation]
ATXMEGA128B3-AU datasheet
 
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Features
High-performance, low-power Atmel
Nonvolatile program and data memories
– 64K - 128KBytes of in-system self-programmable flash
– 4K - 8KBytes boot section
– 2KBytes EEPROM
– 4K - 8KBytes internal SRAM
Peripheral Features
– Two-channel DMA controller
– Four-channel event system
– Two 16-bit timer/counters
One timer/counter with 4 output compare or input capture channels
One timer/counter with 2 output compare or input capture channels
High resolution extensions one timer/counter
Advanced waveform extension (AWeX) on timer/counter
Split mode on timer/counter
– One USB device interface
USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
32 Endpoints with full configuration flexibility
– One USART with IrDA support
– AES and DES crypto engine
– CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3) generator
– One two-wire interface with dual address match (I
– One serial peripheral interface (SPI)
– 16-bit Real Time Counter (RTC) with separate oscillator
– Liquid Crystal Display
4x25 segment driver
Built in contrast control
ASCII character mappingGra
Flexible SWAP of segment and common terminals buses
– One eight-channel, 12-bit, 300 thousand SPS Analog to Digital Converter
– Two Analog Comparators with window compare function, and current source feature
– External interrupts on all General Purpose I/O pins
– Programmable watchdog timer with separate on-chip ultra low power oscillator
®
– QTouch
library support
Capacitive touch buttons, sliders and wheels
Special microcontroller features
– Power-on reset and programmable brown-out detection
– Internal and external clock options with PLL
– Programmable multilevel interrupt controller
– Five sleep modes
– Programming and debug interfaces
JTAG (IEEE 1149.1 Compliant) interface, including boundary scan
PDI (Program and Debug Interface)
I/O and Packages
– 36 Programmable I/O pins
– 64 - lead TQFP
– 64 - pad QFN
Operating Voltage
– 1.6 – 3.6V
Operating frequency
– 0 – 12MHz from 1.6V
– 0 – 32MHz from 2.7V
®
®
®
AVR
XMEGA
8/16-bit Microcontroller
2
C and SMBus compatible)
8/16-bit Atmel
XMEGA B3
Microcontroller
ATxmega128B3
ATxmega64B3
8074B–AVR–02/12

ATXMEGA128B3-AU Summary of contents

  • Page 1

    ... TQFP – pad QFN • Operating Voltage – 1.6 – 3.6V • Operating frequency – 0 – 12MHz from 1.6V – 0 – 32MHz from 2.7V ® ® ® AVR XMEGA 8/16-bit Microcontroller 2 C and SMBus compatible) 8/16-bit Atmel XMEGA B3 Microcontroller ATxmega128B3 ATxmega64B3 8074B–AVR–02/12 ...

  • Page 2

    ... Board control Sensor control • • White goods Optical 1. Ordering Information Ordering Code Flash (Bytes) EEPROM (Bytes) SRAM (Bytes) ATxmega128B3-AU 128K + 8K ATxmega64B3-AU 64K + 4K ATxmega128B3-MH 128K + 8K ATxmega64B3-MH 64K + 4K Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. ...

  • Page 3

    Pinout/Block Diagram Figure 2-1. Block diagram and pinout PC0 1 PC1 2 PC2 3 PC3 4 PC4 5 PC5 6 PC6 7 PC7 8 GND 9 VCC 10 PD0 11 PD1 12 PDI / RESET 13 PDI 14 GND ...

  • Page 4

    Overview The Atmel peripheral-rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the Atmel AVR XMEGA B3 device achieves throughputs CPU approaching one million instructions per second (MIPS) per ...

  • Page 5

    RISC CPU with in-system, self-programmable flash, the Atmel XMEGA pow- erful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. The atmel AVR XMEGA B3 devices are supported with ...

  • Page 6

    Block Diagram Figure 3-1. XMEGA B3 Block Diagram VCC/10 Int. Refs. Tempref AREFB ADCB ACB PB[0..7] / PORT B (8) JTAG 8074B–AVR–02/12 PR[0..1] XTAL1 / TOSC1 XTAL2 / TOSC2 Oscillator PORT R (2) Circuits/ Clock Generation EVENT ROUTING NETWORK ...

  • Page 7

    ... Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading • XMEGA • XMEGA Application Notes This device data sheet only contains part specific information with a short description of each peripheral and module. The XMEGA B Manual describes the modules and peripherals in depth. ...

  • Page 8

    AVR CPU 6.1 Features • 8/16-bit, high-performance Atmel AVR RISC CPU – 142 instructions – Hardware multiplier • 32x8-bit registers directly connected to the ALU • Stack in RAM • Stack pointer accessible in I/O memory space • Direct ...

  • Page 9

    The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information ...

  • Page 10

    Hardware Multiplier The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware mul- tiplier supports different variations of signed and unsigned integer and fractional numbers: •Multiplication of unsigned integers •Multiplication of signed integers •Multiplication ...

  • Page 11

    During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program memory, ...

  • Page 12

    Memories 7.1 Features • Flash program memory – One linear address space – In-system programmable – Self-programming and boot loader support – Application section for application code – Application table section for application code or data storage – Boot ...

  • Page 13

    Flash Program Memory The Atmel for program storage. The flash memory can be accessed for read and write from an external pro- grammer through the PDI or from application software running in the device. All AVR CPU instructions are ...

  • Page 14

    ... The production signature row cannot be written or erased, but it can be read from application software and external programmers. Table 7-1. ATxmega64B3 ATxmega128B3 7.3.5 User Signature Row The user signature row is a separate memory section that is fully accessible (read and write) from application software and external programmers one flash page in size, and is meant for static user parameter storage, such as calibration data, custom serial number, identification numbers, random number seeds, etc ...

  • Page 15

    ... EEPROM page load (write) takes one cycle, and three cycles are required for read. For burst read, new data are available every second cycle. Refer to the instruction sum- mary for more details on instructions and instruction timing. 8074B–AVR–02/12 Data Memory Map (Hexadecimal address) ATxmega128B3 Byte Address 0 I/O Registers (4K) ...

  • Page 16

    ... Table 7-3. Devices EEPROM Size ATxmega64B3 2K ATxmega128B3 2K 8074B–AVR–02/12 shows the Flash Program Memory organization. Flash write and erase Number of words and pages in the flash. Page Size FWORD ...

  • Page 17

    DMAC – Direct Memory Access Controller 8.1 Features • Allows high speed data transfers with minimal CPU intervention – from data memory to data memory – from data memory to peripheral – from peripheral to data memory – from ...

  • Page 18

    Event System 9.1 Features • System for direct peripheral-to-peripheral communication and signaling • Peripherals can directly send, receive, and react to peripheral events – CPU and DMA controller independent operation – 100% predictable signal timing – Short and guaranteed ...

  • Page 19

    Figure 9-1. The event routing network consists of four software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow for up to four parallel event configurations and routings. The maximum routing latency is ...

  • Page 20

    System Clock and Clock options 10.1 Features • Fast start-up time • Safe run-time clock switching • Internal oscillators: – 32MHz run-time calibrated oscillator – 2MHz run-time calibrated oscillator – 32.768kHz calibrated oscillator – 32kHz ultra low power (ULP) ...

  • Page 21

    Figure 10-1. The Clock system, clock sources and clock distribution. Brown-out Detector 10.3 Clock Sources The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock sources can be directly enabled and ...

  • Page 22

    Ultra Low Power Internal Oscillator This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low power clock source, and it is not designed for high accuracy.The oscillator employs a ...

  • Page 23

    PLL with 1x-31x Multiplication Factor The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user-selectable multiplication factor of from 1 to 31. In combination with the pres- calers, this ...

  • Page 24

    Power Management and Sleep Modes 11.1 Features • Power management for adjusting power consumption and functions • Five sleep modes – Idle – Power down – Power save – Standby – Extended standby • Power reduction register to disable ...

  • Page 25

    Power-down Mode In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are ...

  • Page 26

    System Control and Reset 12.1 Features • Reset the microcontroller and set it to initial state when a reset source goes active • Multiple reset sources that cover different situations – Power-on reset – External reset – Watchdog reset ...

  • Page 27

    Reset Sources 12.4.1 Power-on Reset A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the V CC sequence. The POR is also activated to power down the device properly when the V ...

  • Page 28

    WDT – Watchdog Timer 13.1 Features • Issues a device reset if the timer is not reset before its timeout period • Asynchronous operation from dedicated oscillator • 1kHz output of the 32kHz ultra low power oscillator • 11 ...

  • Page 29

    Interrupts and Programmable Multilevel Interrupt Controller 14.1 Features • Short and predictable interrupt response time • Separate interrupt configuration and vector address for each interrupt • Programmable multilevel interrupt controller – Interrupt prioritizing according to level and vector address ...

  • Page 30

    Table 14-1. Reset and Interrupt Vectors (Continued) Program Address (Base Address) Source 0x014 RTC_INT_base 0x018 TWIC_INT_base 0x01C TCC0_INT_base 0x028 TCC1_INT_base 0x030 SPIC_INT_vect 0x032 USARTC0_INT_base 0x03E USB_INT_base 0x046 LCD_INT_base 0x048 AES_INT_vect 0x04A NVM_INT_base 0x04E PORTB_INT_base 0x052 ACB_INT_base 0x058 ADCB_INT_base 0x060 PORTD_INT_base ...

  • Page 31

    I/O Ports 15.1 Features • 36 General purpose input and output pins with individual configuration • Output driver with configurable driver and pull settings: – Totem-pole – Wired-AND – Wired-OR – Bus-keeper – Inverted I/O • Input with synchronous ...

  • Page 32

    Output Driver All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to reduce electromagnetic emission. 15.3.1 Push-pull Figure 15-1. I/O configuration - Totem-pole 15.3.2 Pull-down Figure 15-2. I/O configuration - Totem-pole ...

  • Page 33

    Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’. Figure 15-4. I/O configuration - ...

  • Page 34

    Input sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 15-7. Input sensing system overview INVERTED I/O When a pin is configured with inverted I/O, the ...

  • Page 35

    T/C – 16-bit Timer/Counter Type 0 and 1 16.1 Features • Two 16-bit timer/counters – One timer/counter of type 0 – One timer/counter of type 1 • 32-bit Timer/Counter support by cascading two timer/counters • four compare ...

  • Page 36

    A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system. The event system can also be used for direction control and capture trig- ger or to synchronize operations. There are two ...

  • Page 37

    TC2 –16-bit Timer/Counter Type 2 17.1 Features • A system of two eight-bit timer/counters – Low-byte timer/counter – High-byte timer/counter • Eight compare channels – Four compare channels for the low-byte timer/counter – Four compare channels for the high-byte ...

  • Page 38

    AWeX – Advanced Waveform Extension 18.1 Features • Waveform output with complementary output from each compare channel • Four dead-time insertion (DTI) units – 8-bit resolution – Separate high and low side dead-time setting – Double buffered dead time ...

  • Page 39

    Hi-Res – High Resolution Extension 19.1 Features • Increases waveform generator resolution bits) • Supports frequency, single-slope PWM, and dual-slope PWM generation • Supports the AWeX when this is used for the same timer/counter 19.2 ...

  • Page 40

    RTC – 16-bit Real-Time Counter 20.1 Features • 16-bit resolution • Selectable clock source – 32.768kHz external crystal – External clock – 32.768kHz internal oscillator – 32kHz internal ULP oscillator • Programmable 10-bit clock prescaling • One compare register ...

  • Page 41

    USB – Universal Serial Bus Interface 21.1 Features • One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface • Integrated on-chip USB transceiver, no external components needed • 16 endpoint addresses with full endpoint flexibility ...

  • Page 42

    The USB module has built-in direct memory access (DMA), and will read/write data from/to the SRAM when a USB transaction takes place. To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, ...

  • Page 43

    TWI – Two Wire Interface 22.1 Features • One two-wire interface peripheral • Bidirectional, two-wire communication interface – Phillips I – System Management Bus (SMBus) compatible • Bus master and slave operation supported – Slave operation – Single bus ...

  • Page 44

    It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external TWI bus driver. This can be used for applications where the device operates from a different V PORTC ...

  • Page 45

    SPI – Serial Peripheral Interface 23.1 Features • One SPI peripheral • Full-duplex, three-wire synchronous data transfer • Master or slave operation • Lsb first or msb first data transfer • Eight programmable bit rates • Interrupt flag at ...

  • Page 46

    USART 24.1 Features • One USART peripheral • Full-duplex operation • Asynchronous or synchronous operation – Synchronous clock rates up to 1/2 of the device clock frequency – Asynchronous clock rates up to 1/8 of the device clock frequency ...

  • Page 47

    IRCOM – IR Communication Module 25.1 Features • Pulse modulation/demodulation for infrared communication • IrDA compatible for baud rates up to 115.2kbps • Selectable pulse modulation scheme – 3/16 of the baud rate period – Fixed pulse period, 8-bit ...

  • Page 48

    AES and DES Crypto Engine 26.1 Features • Data Encryption Standard (DES) CPU instruction • Advanced Encryption Standard (AES) crypto module • DES Instruction – Encryption and decryption – DES supported – Encryption/decryption in 16 CPU clock cycles per ...

  • Page 49

    CRC – Cyclic Redundancy Check Generator 27.1 Features • Cyclic redundancy check (CRC) generation and checking for – Communication data – Program or data in flash memory – Data in SRAM and I/O memory space • Integrated with flash ...

  • Page 50

    LCD - Liquid Crystal Display Controller 28.1 Features • Display capacity segments and common terminals • Supports GPIO's • Shadow display memory gives full freedom in segment update • ASCII ...

  • Page 51

    ADC – 12-bit Analog to Digital Converter 29.1 Features • One Analog to Digital Converter (ADC) • 12-bit resolution • 300 thousand samples per second – Down to 2.3µs conversion time with 8-bit resolution – Down to ...

  • Page 52

    Figure 29-1. ADC overview ADC0 • • • ADC15 Internal signals ADC0 • • • ADC7 Internal 1.00V Internal VCC/1.6V Internal VCC/2 The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (prop- agation delay) ...

  • Page 53

    AC – Analog Comparator 30.1 Features • Two Analog Comparators (AC) • Selectable hysteresis – No – Small – Large • Analog comparator output available on pin • Flexible input selection – All pins on the port – Bandgap ...

  • Page 54

    Figure 30-1. Analog comparator overview Pin Input Pin Input Voltage Scaler Bandgap Pin Input Pin Input The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 30-2. Analog ...

  • Page 55

    Programming and Debugging 31.1 Features • Programming – External programming through PDI or JTAG interfaces – Boot loader support for programming through any communication interface • Debugging – Nonintrusive, real-time, on-chip debug system – No software or hardware resources ...

  • Page 56

    Pinout and Pin Functions The device pinout is shown in I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions ...

  • Page 57

    Communication functions SCL SDA SCLIN SCLOUT SDAIN SDAOUT XCKn RXDn TXDn SS MOSI MISO SCK D- D+ 32.1.7 Oscillators, Clock and Event TOSCn XTALn CLKOUT EVOUT RTCOUT 32.1.8 Debug/System functions RESET PDI_CLK PDI_DATA TCK TDI TDO TMS 8074B–AVR–02/12 Serial ...

  • Page 58

    Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head ...

  • Page 59

    Table 32-4. Program and Debug functions PROG PIN # INTERRUPT PDI 13 RESET 14 Table 32-5. LCD (1)(2) (1) LCD PIN # INTERRUPT GND 15 VCC 16 SEG24 17 SYNC SEG23 18 SYNC SEG22 19 SYNC/ASYNC SEG21 20 SYNC SEG20 ...

  • Page 60

    Table 32-5. LCD (Continued) (1)(2) (1) LCD PIN # INTERRUPT COM1 50 COM2 51 COM3 52 Notes: 1. Pin mapping of all Segment terminals (SEGn) can be optionnaly swapped. Interrupt, GPIO and Blink functions will be auto- matically swapped. 2. ...

  • Page 61

    Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA B3. For complete register description and summary for each peripheral module, refer to the XMEGA B Manual. Base Address 0x0000 0x0010 ...

  • Page 62

    Instruction Set Summary Mnemonics Operands Description ADD Rd, Rr Add without Carry ADC Rd, Rr Add with Carry ADIW Rd, K Add Immediate to Word SUB Rd, Rr Subtract without Carry SUBI Rd, K Subtract Immediate SBC Rd, Rr ...

  • Page 63

    Mnemonics Operands Description CALL k call Subroutine RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare with Immediate SBRC Rr, b Skip if Bit in Register ...

  • Page 64

    Mnemonics Operands Description LD Rd, -Y Load Indirect and Pre-Decrement LDD Rd, Y+q Load Indirect with Displacement LD Rd, Z Load Indirect LD Rd, Z+ Load Indirect and Post-Increment LD Rd, -Z Load Indirect and Pre-Decrement LDD Rd, Z+q Load ...

  • Page 65

    Mnemonics Operands Description LAT Z, Rd Load and Toggle RAM location LSL Rd Logical Shift Left LSR Rd Logical Shift Right ROL Rd Rotate Left Through Carry ROR Rd Rotate Right Through Carry ASR Rd Arithmetic Shift Right SWAP Rd ...

  • Page 66

    Packaging information 35.1 64A PIN 0°~7° Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 ...

  • Page 67

    D Marked Pin TOP VIEW BOTTOM VIEW Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. 2325 Orchard Parkway San Jose, CA ...

  • Page 68

    Electrical Characteristics All typical values are measured 25°C unless other temperature condition is given. All min- imum and maximum values are valid across operating temperature and voltage unless other conditions are given. 36.1 Absolute Maximum Ratings ...

  • Page 69

    The maximum System clock frequency of the Atmel shown in CC 1.8V < V Figure 36-1. Maximum Frequency vs. Vcc 8074B–AVR–02/12 Figure 36-1 on page 69 < 2.7V. CC MHz 32 Safe Operating Area 12 1.6 1.8 ...

  • Page 70

    DC Characteristics Table 36-4. Current Consumption for Active and sleep modes Symbol Parameter Condition 32kHz, Ext. Clk 1MHz, Ext. Clk Active Power (1) consumption 2MHz, Ext. Clk 32MHz, Ext. Clk 32kHz, Ext. Clk 1MHz, Ext. Clk Idle Power (1) ...

  • Page 71

    Table 36-5. Current Consumption for modules and peripherals Symbol Parameter ULP oscillator 32.768kHz int. oscillator 2MHz int. oscillator 32MHz int. oscillator PLL Watchdog Timer BOD (2) LCD I CC Internal 1.0V reference Temperature sensor ADC AC DMA USART Flash memory ...

  • Page 72

    Notes: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data 3.0V, Clk = 1MHz External clock without prescaling 25°C unless other conditiond are given. CC SYS 2. ...

  • Page 73

    I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCSMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 36-7. I/O Pin Characteristics Symbol Parameter (1) I ...

  • Page 74

    Liquid Crystal Display characteristics Table 36-8. Liquid Crystal Display characteristics Symbol Parameter SEG Segment Terminal Pins COM Common Terminal Pins f LCD Frame Frequency Frame C Flying Capacitor Flying Contrast Contrast Adjustement V LCD BIAS2 LCD Regulated Voltages BIAS1 ...

  • Page 75

    Table 36-10. Clock and timing. Symbol Parameter Clk ADC Clock frequency ADC f Sample rate ClkADC f Sample rate ADC Sampling Time Conversion time (latency) Start-up time ADC settling time Table 36-11. Accuracy characteristics. Symbol Parameter RES Resolution (1) INL ...

  • Page 76

    Table 36-11. Accuracy characteristics. (Continued) Symbol Parameter Gain Error Gain Error Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 2. Unless otherwise noted all linearity, offset ...

  • Page 77

    Analog Comparator Characteristics Table 36-13. Analog Comparator characteristics. Symbol Parameter V Input Offset Voltage off I Input Leakage Current lk Input voltage range AC startup time V Hysteresis, None hys1 V Hysteresis, Small hys2 V Hysteresis, Large hys3 t ...

  • Page 78

    Brownout Detection Characteristics Table 36-15. Brownout Detection Characteristics Symbol Parameter BOD level 0 falling Vcc BOD level 1 falling Vcc BOD level 2 falling Vcc BOD level 3 falling Vcc BOD level 4 falling Vcc BOD level 5 falling ...

  • Page 79

    Flash and EEPROM Memory Characteristics Table 36-18. Endurance and Data Retention Symbol Parameter Flash EEPROM Table 36-19. Programming time Symbol Parameter Chip Erase Flash EEPROM Notes: 1. Programming is timed from the 2MHz internal oscillator. 2. EEPROM is not ...

  • Page 80

    Calibrated 2MHz RC Internal Oscillator characteristics Table 36-21. Calibrated 2MHz Internal Oscillator characteristics Symbol Parameter Frequency range Factory calibrated frequency Factory calibration accuracy User calibration accuracy DFLL calibration stepsize 36.14.3 Calibrated and tunable 32MHz Internal Oscillator characteristics Table 36-22. ...

  • Page 81

    External Clock Characteristics Figure 36-3. External Clock Drive Waveform Table 36-25. External Clock used as System Clock without prescaling Symbol Parameter (1) 1/t Clock Frequency CK t Clock Period CK t Clock High Time CH t Clock Low Time ...

  • Page 82

    Table 36-26. External Clock with prescaler Symbol Parameter (2) 1/t Clock Frequency CK t Clock Period CK t Clock High Time CH t Clock Low Time CL t Rise Time (for maximum frequency Fall Time (for maximum frequency) ...

  • Page 83

    Symbol Parameter (1) Negative impedance R Q Start-up time Parasitic capacitance C XTAL1 Parasitic capacitance C XTAL2 Parasitic capacitance load C LOAD Note: 1. Numbers for negative impedance are not tested but guaranteed from design and characterization. 8074B–AVR–02/12 Condition 0.4MHz ...

  • Page 84

    External 32.768kHz crystal oscillator and TOSC characteristics Table 36-28. External 32.768kHz crystal oscillator and TOSC characteristics Symbol Parameter Recommended crystal equivalent ESR/R1 series resistance (ESR) C Input capacitance between TOSC pins IN_TOSC Recommended Safety factor Long term Jitter (SIT) ...

  • Page 85

    SPI characteristics Figure 36-5. SPI interface requirements in master mode (CPOL = 0) (CPOL = 1) (Data Input) (Data Output) Figure 36-6. SPI timing requirements in slave mode (CPOL = 0) (CPOL = 1) (Data Input) (Data Output) 8074B–AVR–02/12 ...

  • Page 86

    Table 36-29. SPI Timing characteristics and requirements Symbol Parameter t SCK Period SCK t SCK high/low width SCKW t SCK Rise time SCKR t SCK Fall time SCKF t MISO setup to SCK MIS t MISO hold after SCK MIH ...

  • Page 87

    Two-Wire Interface Characteristics Table 2-1 describes the requirements for devices connected to the Two Wire Serial Bus. The XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 36-7. Two-Wire Interface Bus ...

  • Page 88

    Table 36-30. Two Wire Serial Bus Characteristics (Continued) Symbol Parameter t Data hold time HD;DAT t Data setup time SU;DAT t Setup time for STOP condition SU;STO Bus free time between a STOP and START t BUF condition Notes: 1. ...

  • Page 89

    Typical Characteristics 37.1 Current consumption 37.1.1 Active mode supply current Figure 37-1. Active supply current vs. frequency. Figure 37-2. Active supply current vs. frequency. 8074B–AVR–02/ 1MHz external clock 25°C SYS 1000 900 800 ...

  • Page 90

    Figure 37-3. Active mode supply current vs. V Figure 37-4. Active mode supply current vs. V 8074B–AVR–02/ 2MHz internal oscillator SYS 2100 1900 1700 1500 1300 1100 900 700 500 1.6 1.8 2 2.2 2 ...

  • Page 91

    Idle mode supply current Figure 37-5. Idle mode supply current vs. frequency. Figure 37-6. Idle mode supply current vs. frequency. 8074B–AVR–02/ 1MHz external clock 25°C SYS 180 160 140 120 100 80 60 ...

  • Page 92

    Figure 37-7. Idle mode supply current vs. V Figure 37-8. Idle mode supply current vs. V 8074B–AVR–02/ 32.768kHz internal oscillator SYS 34.5 33.75 33 32.25 31.5 30.75 30 29.25 28.5 27.75 27 1.6 1.8 2 2.2 2.4 ...

  • Page 93

    Figure 37-9. Idle mode current vs. V 37.1.3 Power-down mode supply current Figure 37-10. Power-down mode supply current vs. V 8074B–AVR–02/ 32MHz internal oscillator SYS 5800 5300 4800 4300 3800 3300 2800 2300 1800 1.6 ...

  • Page 94

    Figure 37-11. Power-down mode supply current vs. V 37.2 I/O Pin Characteristics 37.2.1 Pull-up Figure 37-12. I/O pin pull-up resistor current vs. input voltage. 8074B–AVR–02/12 Watchdog and sampled BOD enabled 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 ...

  • Page 95

    Figure 37-13. I/O pin pull-up resistor current vs. input voltage. Figure 37-14. I/O pin pull-up resistor current vs. pin voltage. 8074B–AVR–02/ 3.0V CC 140 120 100 0.3 0.6 0.9 1.2 . ...

  • Page 96

    Output Voltage vs. Sink/Source Current Figure 37-15. I/O pin output voltage vs. source current. Figure 37-16. I/O pin output voltage vs. source current. 8074B–AVR–02/ 1.8V CC 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 ...

  • Page 97

    Figure 37-17. I/O pin output voltage vs. source current. Figure 37-18. I/O pin output voltage vs. sink current. 8074B–AVR–02/ 3.3V CC 3.5 3.25 3 2.75 2.5 2.25 2 1.75 1.5 1.25 1 -20 -18 -16 -14 -12 ...

  • Page 98

    Figure 37-19. I/O pin output voltage vs. sink current. Figure 37-20. I/O pin output voltage vs. sink current. 8074B–AVR–02/ 3.0V CC 0.6 0.54 0.48 0.42 0.36 0.3 0.24 0.18 0.12 0. ...

  • Page 99

    Thresholds and Hysteresis Figure 37-21. I/O pin input threshold voltage vs. V 1.8 1.6 1.4 1.2 0.8 Figure 37-22. I/O pin input threshold voltage vs. V 1.7 1.5 1.3 1.1 0.9 0.7 0.5 8074B–AVR–02/ I/O pin read ...

  • Page 100

    Figure 37-23. I/O pin input hysteresis vs. V 37.3 ADC Characteristics Figure 37-24. INL error vs. external V 8074B–AVR–02/12 350 300 250 200 150 100 1.6 1.8 2.0 2.2 REF ° 3.6V, external reference ...

  • Page 101

    Figure 37-25. INL error vs. sample rate. Figure 37-26. INL error vs. input code. 8074B–AVR–02/12 ° 3.6V 3.0V external CC REF 0.70 0.65 0.60 0.55 Differential mode 0.50 0.45 0.40 0.35 Single-ended ...

  • Page 102

    Figure 37-27. DNL error vs. external V Figure 37-28. DNL error vs. sample rate. 8074B–AVR–02/12 . REF ° 3.6V, external reference CC 0.70 0.65 0.60 Single-ended unsigned mode 0.55 0.50 0.45 0.40 0.35 0.30 ...

  • Page 103

    Figure 37-29. DNL error vs. input code. Figure 37-30. Gain error vs. V 8074B–AVR–02/12 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 512 1024 1536 ADC input code . REF ° 3.6V, ...

  • Page 104

    Figure 37-31. Gain error vs. V Figure 37-32. Offset error vs. V 8074B–AVR–02/ ° external 1.0V, ADC sample rate = 300ksps REF - Single-ended signed -6 Single-ended unsigned mode ...

  • Page 105

    Figure 37-33. Gain error vs. temperature. Figure 37-34. Offset error vs. V 8074B–AVR–02/ 3.0V external 2.0V CC REF - Single-ended signed mode - -10 Single-ended unsigned mode -11 -12 -13 ...

  • Page 106

    Analog Comparator Characteristics Figure 37-35. Analog comparator hysteresis vs. V Figure 37-36. Analog comparator hysteresis vs. V 8074B–AVR–02/12 . High-speed mode, small hysteresis 1.6 1.8 2 2.2 2.4 ...

  • Page 107

    Figure 37-37. Analog comparator propagation delay vs Figure 37-38. Analog comparator current consumption vs. V 8074B–AVR–02/12 . High speed mode 1.6 1.8 2 2.2 2.4 High-speed mode. 290 270 ...

  • Page 108

    Figure 37-39. Analog comparator voltage scaler vs. SCALEFAC. Figure 37-40. Analog comparator offset voltage vs. Common mode voltage. 8074B–AVR–02/12 ° 3.5 3 2.5 2 1 High-speed mode. ...

  • Page 109

    Figure 37-41. Analog comparator current source vs. Calibration. 37.5 Internal 1.0V reference Characteristics Figure 37-42. ADC/DAC Internal 1.0V reference vs. temperature. 8074B–AVR–02/ 3.0V, double mode CC 12 11.5 11 10.5 10 9 ...

  • Page 110

    BOD Characteristics Figure 37-43. BOD current consumption vs. V Figure 37-44. BOD current consumption vs. V 8074B–AVR–02/12 . Continuous mode, BOD level = 1.6V 150 140 130 120 110 100 90 80 1.8 2 2.2 2.4 . Sampled mode, ...

  • Page 111

    Figure 37-45. BOD thresholds vs. temperature. Figure 37-46. BOD thresholds vs. temperature. 8074B–AVR–02/12 . BOD level = 1.6V 1.626 1.624 1.622 1.62 1.618 1.616 1.614 1.612 1.61 1.608 1.606 1.604 -40 -30 -20 - Temperature [°C] . BOD ...

  • Page 112

    Figure 37-47. BOD thresholds vs. temperature. 37.7 External Reset Characteristics Figure 37-48. Minimum Reset pin pulse width vs. V 8074B–AVR–02/12 . BOD level = 3.0V 3.07 3.06 3.05 3.04 3.03 3.02 3.01 3 -40 -30 -20 - Temperature ...

  • Page 113

    Figure 37-49. Reset pin pull-up resistor current vs. reset pin voltage. Figure 37-50. Reset pin pull-up resistor current vs. reset pin voltage. 8074B–AVR–02/ 1. 0.2 0.4 0.6 ...

  • Page 114

    Figure 37-51. Reset pin pull-up resistor current vs. reset pin voltage. Figure 37-52. Reset pin input threshold voltage vs. V 8074B–AVR–02/ 3.3V CC 140 120 100 0.3 0.6 0.9 1.2 . ...

  • Page 115

    Figure 37-53. Reset pin input threshold voltage vs. V 8074B–AVR–02/ Reset pin read as “0” IL 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 1.6 1.8 2 2.2 2.4 XMEGA 2.6 2.8 3 3.2 ...

  • Page 116

    Oscillator Characteristics 37.8.1 32.768kHz Internal Oscillator Figure 37-54. 32.768kHz internal oscillator frequency vs. temperature. Figure 37-55. 32.768kHz ULP internal oscillator frequency vs. temperature. 8074B–AVR–02/12 32.83 32.82 32.81 32.8 32.79 32.78 32.77 32.76 32.75 32.74 32.73 -40 -30 -20 -10 ...

  • Page 117

    Figure 37-56. 32.768kHz internal oscillator calibration step size. Figure 37-57. 32.768kHz internal oscillator frequency vs. calibration value. 8074B–AVR–02/12 ° ° - 0.01 0.005 0.000 -0.005 -0.01 -0.015 -0.02 -0.025 ...

  • Page 118

    Internal Oscillator Figure 37-58. 2MHz internal oscillator frequency vs. temperature. Figure 37-59. 2MHz internal oscillator frequency vs. temperature. 8074B–AVR–02/12 . DFLL disabled 2.16 2.14 2.12 2.1 2.08 2.06 2.04 2.02 2.00 1.98 1.96 -45 -35 -25 -15 -5 ...

  • Page 119

    Figure 37-60. 2MHz internal oscillator CALA calibration step size. Figure 37-61. 2MHz internal oscillator CALB calibration step size. 8074B–AVR–02/ -0.14 -0.15 -0.16 -0.17 -0.18 -0.19 -0.2 -0.21 -0.22 -0.23 -0.24 -0.25 -0.26 -0. ...

  • Page 120

    Internal Oscillator Figure 37-62. 32MHz internal oscillator frequency vs. temperature. Figure 37-63. 32MHz internal oscillator frequency vs. temperature. 8074B–AVR–02/12 . DFLL disabled 35.5 35 34.5 34 33.5 33 32.5 32 31.5 31 -45 -35 -25 - ...

  • Page 121

    Figure 37-64. 32MHz internal oscillator CALA calibration step size. Figure 37-65. 32MHz internal oscillator CALB calibration step size. 8074B–AVR–02/ 3.0V CC -0.1 -0.12 -0.14 -0.16 -0.18 -0.2 -0.22 -0.24 -0.26 -0.28 -0 ...

  • Page 122

    Figure 37-66. 32MHz internal oscillator frequency vs. CALA calibration value. Figure 37-67. 32MHz internal oscillator frequency vs. CALB calibration value. 8074B–AVR–02/ 3. ...

  • Page 123

    Figure 37-68. 48MHz internal oscillator frequency vs. temperature. Figure 37-69. 48MHz internal oscillator frequency vs. temperature. 8074B–AVR–02/12 DFLL disabled -45 -35 -25 - ...

  • Page 124

    Figure 37-70. 32MHz internal oscillator CALA calibration step size. Figure 37-71. 48MHz internal oscillator frequency vs. CALA calibration value. 8074B–AVR–02/12 Using 48MHz calibration value from signature row, V 0.80 0.60 0.40 0.20 0.00 -0.20 -0.40 -0. ...

  • Page 125

    PDI characteristics Figure 37-72. Maximum PDI frequency vs. V 8074B–AVR–02/12 20.5 20.0 19.5 19.0 18.5 18.0 17.5 17.0 1.6 1.8 2 2.2 2.4 XMEGA 2.6 2.8 3 3.2 3.4 V [V] CC 25°C -40°C 85°C 3.6 ...

  • Page 126

    LCD Characteristics Figure 37-73. I Figure 37-74. I 8074B–AVR–02/12 vs. Frame Rate CC 32Hz Low P ower Frame Rate from 32.768KHz TOSC, w/ and w/o pixel load ...

  • Page 127

    Figure 37-75. I Figure 37-76. I 8074B–AVR–02/12 vs. Frame Rate CC 0pF load vs. Contrast CC 32Hz Low Power Frame Rate from 32.768KHz TOSC, w/o pixel load, V 7.5 7 ...

  • Page 128

    Figure 37-77. I Figure 37-78. Psave LCD LP 32Hz vs. Temperature 8074B–AVR–02/12 vs. Contrast CC 32Hz Low Power Frame Rate from 32.768KHz TOSC, w/o pixel load, V 7.5 7 6.5 6 5.5 5 4.5 4 3.5 3 -32 -23 -14 ...

  • Page 129

    Figure 37-79. Psave LCD LP 32Hz vs. Temperature Figure 37-80. Psave vs. Temperature 8074B–AVR–02/12 RTC, WDT, BOD sampled 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 -40 -30 -20 - RTC, WDT, BOD sampled 0.3 0.275 ...

  • Page 130

    ... Errata 38.1 ATxmega64B3, ATxmega128B3 38.1.1 Rev. C • JTAG revision • AWeX fault protection restore is not done correct in Pattern Generation Mode 1. JTAG revision is unchanged between rev. B and rev AWeX fault protection restore is not done correctly in Pattern Generation Mode When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN is restored according to the corresponding enabled DTI channels ...

  • Page 131

    Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 39.1 8074B –02/ 39.2 8074A ...

  • Page 132

    Table of contents Features ..................................................................................................... 1 1 Ordering Information ............................................................................... 2 2 Pinout/Block Diagram .............................................................................. 3 3 Overview ................................................................................................... 4 4 Resources ................................................................................................. 7 5 Capacitive touch sensing ........................................................................ 7 6 AVR CPU ................................................................................................... 8 7 Memories ................................................................................................ 12 8 ...

  • Page 133

    Event System ......................................................................................... 18 10 System Clock and Clock options ......................................................... 20 11 Power Management and Sleep Modes ................................................. 24 12 System Control and Reset .................................................................... 26 13 WDT – Watchdog Timer ......................................................................... 28 14 Interrupts and Programmable Multilevel ...

  • Page 134

    TC2 –16-bit Timer/Counter Type 2 ........................................................ 37 18 AWeX – Advanced Waveform Extension ............................................. 38 19 Hi-Res – High Resolution Extension .................................................... 39 20 RTC – 16-bit Real-Time Counter ........................................................... 40 21 USB – Universal Serial Bus Interface ................................................... ...

  • Page 135

    LCD - Liquid Crystal Display Controller .............................................. 50 29 ADC – 12-bit Analog to Digital Converter ............................................ – Analog Comparator ...................................................................... 53 31 Programming and Debugging .............................................................. 55 32 Pinout and Pin Functions ...................................................................... 56 33 ...

  • Page 136

    ... Pin Characteristics ...........................................................................................94 37.3ADC Characteristics ............................................................................................100 37.4Analog Comparator Characteristics .....................................................................106 37.5Internal 1.0V reference Characteristics ...............................................................109 37.6BOD Characteristics ............................................................................................110 37.7External Reset Characteristics ............................................................................112 37.8Oscillator Characteristics .....................................................................................116 37.9PDI characteristics ..............................................................................................125 37.10LCD Characteristics ..........................................................................................126 38.1ATxmega64B3, ATxmega128B3 .........................................................................130 39.18074B –02/12 ......................................................................................................131 39.28074A – 10/11 .....................................................................................................131 XMEGA B3 v ...

  • Page 137

    Atmel Corporation Atmel Asia Limited 2325 Orchard Parkway Unit 1-5 & 16, 19/F San Jose, CA 95131 BEA Tower, Millennium City 5 USA 418 Kwun Tong Road Tel: (+1)(408) 441-0311 Kwun Tong, Kowloon Fax: (+1)(408) 487-2600 HONG KONG www.atmel.com Tel: ...