AT91SAM7S128 ATMEL [ATMEL Corporation], AT91SAM7S128 Datasheet
AT91SAM7S128
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AT91SAM7S128 Summary of contents
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... Internal High-speed Flash – 256 kbytes, organized in 1024 Pages of 256 Bytes (AT91SAM7S256) – 128 kbytes, organized in 512 Pages of 256 Bytes (AT91SAM7S128) – 64 kbytes, organized in 512 Pages of 128 Bytes (AT91SAM7S64) – 32 kbytes, organized in 256 Pages of 128 Bytes (AT91SAM7S321/32) – Single Cycle Access MHz in Worst Case Conditions – ...
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One Parallel Input/Output Controller (PIOA) – Thirty-two (AT91SAM7S256/128/64/321) or twenty-one (AT91SAM7S32) Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up resistor and Synchronous Output ...
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... PC or cellu- lar phone. Their aggressive price point and high level of integration pushes their scope of use far into the cost-sensitive, high-volume consumer market. 2. Configuration Summary of the AT91SAM7S256, AT91SAM7S128, AT91SAM7S64, AT91SAM7S321 and AT91SAM7S32 The AT91SAM7S256, AT91SAM7S128, AT91SAM7S64, AT91SAM7S321 and AT91SAM7S32 differ in memory size, peripheral set and package ...
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Block Diagram Figure 3-1. AT91SAM7S256/128/64/321 Block Diagram TDI TDO JTAG TMS SCAN TCK JTAGSEL System Controller TST FIQ IRQ0-IRQ1 PCK0-PCK2 PLLRC PLL XIN OSC XOUT RCOSC VDDCORE BOD POR VDDCORE NRST DRXD DTXD RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 ...
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Figure 3-2. AT91SAM7S32 Block Diagram TDI TDO TMS TCK JTAGSEL System Controller TST FIQ IRQ0 PCK0-PCK2 PLLRC PLL XIN OSC XOUT VDDCORE BOD POR VDDCORE NRST DRXD DTXD RXD0 TXD0 SCK0 RTS0 CTS0 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK ...
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Signal Description Table 4-1. Signal Description List Signal Name Function VDDIN Voltage and ADC Regulator Power Supply Input VDDOUT Voltage Regulator Output VDDFLASH Flash Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL GND Ground ...
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Table 4-1. Signal Description List (Continued) Signal Name Function DDM USB Device Port Data - DDP USB Device Port Data + SCK0 - SCK1 Serial Clock TXD0 - TXD1 Transmit Data RXD0 - RXD1 Receive Data RTS0 - RTS1 Request ...
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Table 4-1. Signal Description List (Continued) Signal Name Function TWD Two-wire Serial Data TWCK Two-wire Serial Clock AD0-AD3 Analog Inputs AD4-AD7 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0-PGMEN2 Programming Enabling PGMM0-PGMM3 Programming Mode PGMD0-PGMD15 Programming Data PGMRDY Programming ...
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Package and Pinout The AT91SAM7S256/128/64/321 are available in a 64-lead LQFP package. The AT91SAM7S32 is available in a 48-lead LQFP package. 5.1 64-lead LQFP Mechanical Overview Figure 5-1 tion is given in the section Mechanical Characteristics of the full ...
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LQFP Mechanical Overview Figure 5-1 tion is given in the section Mechanical Characteristics of the product datasheet. Figure 5-2. 5.4 48-lead LQFP Pinout Table 5-2. AT91SAM7S32 Pinout in 48-lead LQFP Package 1 ADVREF 13 2 GND 14 3 ...
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Power Considerations 6.1 Power Supplies The AT91SAM7S Series has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDIN ...
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One external 2.2 µF (or 3.3 µF) X7R capacitor must be connected between VDDOUT and GND. Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor ...
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I/O Lines Considerations 7.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven ...
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I/O Line Drive Levels The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive permanently. The remaining I/O lines can draw only 8 mA. However, the total current ...
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Processor and Architecture 8.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs MHz, providing 0.9 MIPS/MHz • Two instruction sets – ARM – Thumb • Three-stage pipeline architecture – Instruction ...
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Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and locking operations – Interrupt generation in case of forbidden operation 8.4 Peripheral DMA Controller ...
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... Kbytes of Flash Memory single plane – – – – – – – – • 64 Kbytes of Fast SRAM – 9.2 AT91SAM7S128 • 128 Kbytes of Flash Memory single plane – – – – – – – – • 32 Kbytes of Fast SRAM – ...
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AT91SAM7S321/32 • 32 Kbytes of Flash Memory single plane – – – – – – – – • 8 Kbytes of Fast SRAM – 9.5 Memory Mapping 9.5.1 Internal SRAM The AT91SAM7S256/128/64/321/32 embeds a high-speed 64/32/16/8/8-Kbyte SRAM bank. After ...
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... The Flash of the AT91SAM7S256 is organized in 1024 pages of 256 bytes. The 262,144 bytes are organized in 32-bit words. • The Flash of the AT91SAM7S128 is organized in 512 pages of 256 bytes. The 131,072 bytes are organized in 32-bit words. • The Flash of the AT91SAM7S64 is organized in 512 pages of 128 bytes. The 65,536 bytes are organized in 32-bit words. • ...
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If a locked-regions erase or program command occurs, the command is aborted and the EFC trigs an interrupt. The 16 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the protection. The command ...
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SAM-BA Boot Assistant The SAM-BA Flash memory. The SAM-BA Boot recovery is performed when the TST pin and the PA0, PA1 and PA2 pins are all tied high. The SAM-BA Boot Assistant is a default Boot Program that provides ...
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System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. Figure 10-1. System Controller Block Diagram (AT91SAM7S256/128/64/321) irq0-irq1 periph_irq[2..14] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd periph_nreset periph_nreset proc_nreset ...
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Figure 10-2. System Controller Block Diagram (AT91SAM7S32) periph_irq[2..14] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd periph_nreset periph_nreset proc_nreset cal gpnvm[0] en BOD POR NRST RCOSC XIN OSC XOUT PLL PLLRC periph_nreset periph_nreset periph_clk[2] dbgu_rxd PA0-PA20 6175BS–ATARM–04-Nov-05 AT91SAM7S Series Summary ...
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System Controller Mapping The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Figure 10-3 figuration user interface is also mapped within this address space. Figure 10-3. ...
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Reset Controller The Reset Controller is based on a power-on reset cell and one brownout detector. It gives the status of the last reset, indicating whether power-up reset, a software reset, a user reset, a watchdog ...
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Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 kHz and 42 kHz • Main Oscillator frequency ranges between 3 and 20 ...
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Power Management Controller The Power Management Controller uses the Clock Generator outputs to provide: • the Processor Clock PCK • the Master Clock MCK • the USB Clock UDPCK (not present on AT91SAM7S32) • all the peripheral clocks, independently ...
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... Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of – Chip ID is 0x270B0940 for AT91SAM7S256 (VERSION 0) – Chip ID is 0x270A0740 for AT91SAM7S128 (VERSION 0) – Chip ID is 0x27090540 for AT91SAM7S64 (VERSION 0) – Chip ID is 0x27080342 for AT91SAM7S321 (VERSION 0) – ...
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Real-time Timer • 32-bit free-running counter with alarm running on prescaled SCLK • Programmable 16-bit prescaler for SLCK accuracy compensation 10.10 PIO Controller • One PIO Controller, controlling 32 I/O lines (21 for AT91SAM7S32) • Fully programmable through set/clear ...
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Peripherals 11.1 Peripheral Mapping Each peripheral is allocated 16 Kbytes of address space. Figure 11-1. User Peripheral Mapping (AT91SAM7S256/128/64/321) 0xFFFA 0000 0xFFFB 0000 0xFFFB 8000 0xFFFC 0000 0xFFFC 4000 0xFFFC C000 0xFFFD 4000 0xFFFD 8000 0xFFFE 0000 AT91SAM7S Series ...
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Figure 11-2. User Peripheral Mapping (AT91SAM7S32) 0xFFFA 0000 0xFFFB 0000 0xFFFB 8000 0xFFFC 0000 0xFFFC 4000 0xFFFC C000 0xFFFD 4000 0xFFFD 8000 0xFFFE 0000 6175BS–ATARM–04-Nov-05 AT91SAM7S Series Summary 0xF000 0000 Reserved 0xFFF9 FFFF TC0, TC1, TC2 Timer/Counter 0, 1 and ...
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Peripheral Multiplexing on PIO Lines The AT91SAM7S Series features one PIO controller, PIOA, that multiplexes the I/O lines of the peripheral set. PIO Controller A controls 32 lines (21 lines for AT91SAM7S32). Each line can be assigned to one ...
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PIO Controller A Multiplexing Table 11-1. Multiplexing on PIO Controller A (AT91SAM7S256/128/64/321) PIO Controller A I/O Line Peripheral A PA0 PWM0 PA1 PWM1 PA2 PWM2 PA3 TWD PA4 TWCK PA5 RXD0 PA6 TXD0 PA7 RTS0 PA8 CTS0 PA9 DRXD ...
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Table 11-2. Multiplexing on PIO Controller A (SAM7S32) PIO Controller A I/O Line Peripheral A PA0 PWM0 PA1 PWM1 PA2 PWM2 PA3 TWD PA4 TWCK PA5 RXD0 PA6 TXD0 PA7 RTS0 PA8 CTS0 PA9 DRXD PA10 DTXD PA11 NPCS0 PA12 ...
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Peripheral Identifiers The AT91SAM7S Series embeds a wide range of peripherals. Identifiers of the AT91SAM7S256/128/64/321. the AT91SAM7S32. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of ...
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Table 11-4. Peripheral Note: 11.5 Serial Peripheral Interface • Supports communication with external serial devices – Four chip selects ...
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Two-wire Interface • Master Mode only • Compatibility with standard two-wire serial memories • One, two or three bytes for slave address • Sequential read/write operations 11.7 USART • Programmable Baud Rate Generator • 9-bit full-duplex synchronous ...
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Three output compare or two input capture • Wide range of functions including: – Frequency measurement – Event counting – Interval measurement – Pulse generation – Delay timing – Pulse Width Modulation – Up/down capabilities • Each channel is ...
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Endpoint 0: 8 bytes – Endpoint 1 and 2: 64 bytes ping-pong – Endpoint 3: 64 bytes – Ping-pong Mode (two memory banks) for bulk endpoints • Suspend/resume logic 11.12 Analog-to-digital Converter • 8-channel ADC • 10-bit 384 Ksamples/sec. ...
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... AT91SAM7S Series Ordering Information Table 12-1. Ordering Information Ordering Code AT91SAM7S256-AU-001 AT91SAM7S128-AU-001 AT91SAM7S64-AU-001 AT91SAM7S321-AU-001 AT91SAM7S32-AU-001 AT91SAM7S Series Summary 40 Package Package Type LQFP 64 Green LQFP 64 Green LQFP 64 Green LQFP 64 Green LQFP 48 Green Temperature ROM Code Revision Operating Range ...
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Revision History Table 12-2. Revision History Doc. Rev Comments First issue - Unqualified on Intranet 6175AS Corresponds to 6175A full datasheet approval loop. Qualified on Intranet. 6175BS Section 9. ”Memory”, on page 17 6175BS–ATARM–04-Nov-05 AT91SAM7S Series Summary updated ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...