ATxmega128D4-AU ATMEL [ATMEL Corporation], ATxmega128D4-AU Datasheet - Page 16

• Manufacturer Part Number: ATxmega128D4-AU
• Description: 8/16-bit Atmel XMEGA D4 Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

7.7.1
7.8
7.9
7.10
7.11
7.12
8135L–AVR–06/12
ATxmega16D4
ATxmega32D4
ATxmega64D4
ATxmega128D4
Devices
Data Memory and Bus Arbitration
Memory Timing
Device ID and Revision
I/O Memory Protection
Flash and EEPROM Page Size
General Purpose I/O Registers
PC size
[bits]
14
15
16
17
The I/O memory address for all peripherals and modules in XMEGA D4 is shown in the
eral Module Address Map” on page
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These reg-
isters can be used for storing global variables and flags, as they are directly bit-accessible using
the SBI, CBI, SBIS, and SBIC instructions.
Since the data memory is organized as four separate sets of memories, the bus masters (CPU,
etc.) can access different memory sections at the same time.
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes
one cycle, and a read from SRAM takes two cycles. EEPROM page load (write) takes one cycle,
and three cycles are required for read. For burst read, new data are available every second
cycle. Refer to the instruction summary for more details on instructions and instruction timing.
Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the
device and the device type. A separate register contains the revision number of the device.
Some features in the device are regarded as critical for safety in some applications. Due to this,
it is possible to lock the I/O register related to the clock system, the event system, and the
advanced waveform extensions. As long as the lock is enabled, all related I/O registers are
locked and they can not be written from the application software. The lock registers themselves
are protected by the configuration change protection mechanism.
The flash program memory and EEPROM data memory are organized in pages. The pages are
word accessible for the flash and byte accessible for the EEPROM.
Table 7-2
Flash write and erase operations are performed on one page at a time, while reading the Flash
is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The
most significant bits in the address (FPAGE) give the page number and the least significant
address bits (FWORD) give the word in the page.
Table 7-2.
Flash size
128K + 8K
16K + 4K
32K + 4K
64K + 4K
[bytes]
shows the Flash Program Memory organization and Program Counter (PC) size.
Number of words and pages in the flash.
Page size
[words]
128
128
128
128
FWORD
Z[6:0]
Z[6:0]
Z[6:0]
Z[8:0]
56.
FPAGE
Z[13:7]
Z[14:7]
Z[15:7]
Z[16:7]
128K
Size
16K
32K
64K
Application
No of pages
128
256
512
64
XMEGA D4
Size
4K
8K
4K
4K
Boot
No of pages
”Periph-
16
16
16
32
16