AT32UC3L064_11 ATMEL [ATMEL Corporation], AT32UC3L064_11 Datasheet - Page 84

• Manufacturer Part Number: AT32UC3L064_11
• Description: 32-bit Atmel AVR Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

10.1.15
10.2
10.2.1
10.2.2
10.2.3
32099HS–12/2011
Rev. D
I/O Pins
Processor and Architecture
FLASHCDW
Power Manager
1. PA17 has low ESD tolerance
1. Hardware breakpoints may corrupt MAC results
2. Privilege violation when using interrupts in application mode with protected system
1. Flash self programming may fail in one wait state mode
1. Clock sources will not be stopped in Static mode if the difference between CPU and
Solution 1: Disable OSC0 by writing a zero to the Oscillator Enable bit in the System Control
Interface (SCIF) Oscillator Control Register (SCIF.OSC0CTRL.OSCEN) before going to a
sleep mode where OSC0 is disabled.
Solution 2: Pull down or up XIN0 or XOUT0 with 1MOhm resistor.
PA17 only tolerates 500V ESD pulses (Human Body Model).
Fix/Workaround
Care must be taken during manufacturing and PCB design.
Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC
instruction.
Fix/Workaround
Place breakpoints on earlier or later instructions.
stack
If the system stack is protected by the MPU and an interrupt occurs in application mode, an
MPU DTLB exception will occur.
Fix/Workaround
Make a DTLB Protection (Write) exception handler which permits the interrupt request to be
handled in privileged mode.
Writes in flash and user pages may fail if executing code is located in address space
mapped to flash, and the flash controller is configured in one wait state mode (the Flash
Wait State bit in the Flash Control Register (FCR.FWS) is one).
Fix/Workaround
Solution 1: Configure the flash controller in zero wait state mode (FCR.FWS=0).
Solution 2: Configure the HMATRIX master 1 (CPU Instruction) to use the unlimited burst
length transfer mode (MCFG1.ULBT=0), and the HMATRIX slave 0 (FLASHCDW) to use
the maximum slot cycle limit (SCFG0.SLOT_CYCLE=255).
PBx division factor is larger than 4
If the division factor between the CPU/HSB and PBx frequencies is more than 4 when enter-
ing a sleep mode where the system RC oscillator (RCSYS) is turned off, the high speed
clock sources will not be turned off. This will result in a significantly higher power consump-
tion during the sleep mode.
Fix/Workaround
AT32UC3L016/32/64
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